2  * Copyright (c) 2017-2018 ARM Limited
5  * SPDX-License-Identifier: Apache-2.0
61 	SMSC9220->MAC_CSR_CMD = cmd;  in smsc_mac_regread()
63 	while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {  in smsc_mac_regread()
66 	*val = SMSC9220->MAC_CSR_DATA;  in smsc_mac_regread()
75 	SMSC9220->MAC_CSR_DATA = val;  in smsc_mac_regwrite()
77 	SMSC9220->MAC_CSR_CMD = cmd;  in smsc_mac_regwrite()
79 	while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {  in smsc_mac_regwrite()
92 		return -1;  in smsc_phy_regread()
97 		return -EBUSY;  in smsc_phy_regread()
107 		return -1;  in smsc_phy_regread()
113 		time_out--;  in smsc_phy_regread()
115 			return -1;  in smsc_phy_regread()
120 		return -ETIMEDOUT;  in smsc_phy_regread()
124 		return -1;  in smsc_phy_regread()
137 		return -1;  in smsc_phy_regwrite()
141 		return -EBUSY;  in smsc_phy_regwrite()
145 		return -1;  in smsc_phy_regwrite()
154 		return -1;  in smsc_phy_regwrite()
159 		time_out--;  in smsc_phy_regwrite()
161 			return -1;  in smsc_phy_regwrite()
166 		return -ETIMEDOUT;  in smsc_phy_regwrite()
200 	uint32_t id = SMSC9220->ID_REV;  in smsc_check_id()
206 		return -1;  in smsc_check_id()
215 		return -1;  in smsc_check_id()
225 	SMSC9220->HW_CFG |= HW_CFG_SRST;  in smsc_soft_reset()
229 		time_out--;  in smsc_soft_reset()
230 	} while (time_out != 0U && (SMSC9220->HW_CFG & HW_CFG_SRST));  in smsc_soft_reset()
233 		return -1;  in smsc_soft_reset()
243 		SMSC9220->HW_CFG = val << 16;  in smsc_set_txfifo()
249 	SMSC9220->INT_EN = 0;  in smsc_init_irqs()
251 	SMSC9220->INT_STS = 0xFFFFFFFF;  in smsc_init_irqs()
254 	SMSC9220->IRQ_CFG = 0x22000111;  in smsc_init_irqs()
262 		return -1;  in smsc_check_phy()
266 		return -1;  in smsc_check_phy()
278 		return -1;  in smsc_reset_phy()
284 		return -1;  in smsc_reset_phy()
314 	hw_cfg = SMSC9220->HW_CFG;  in smsc_establish_link()
317 	SMSC9220->HW_CFG = hw_cfg;  in smsc_establish_link()
322 	SMSC9220->TX_CFG = 0x2 /*TX_CFG_TX_ON*/;  in smsc_enable_xmit()
351 		return -1;  in smsc_init()
355 		return -1;  in smsc_init()
361 	/* threshold to defaults specified. */  in smsc_init()
362 	SMSC9220->AFC_CFG = 0x006E3740;  in smsc_init()
364 	/* May need to initialize EEPROM/read MAC from it on real HW. */  in smsc_init()
367 	SMSC9220->GPIO_CFG = 0x70070000;  in smsc_init()
374 		return -1;  in smsc_init()
378 		return -1;  in smsc_init()
392 	/* bit [12] of BCONTROL seems self-clearing. */  in smsc_init()
396 	/* Interrupt threshold */  in smsc_init()
397 	SMSC9220->FIFO_INT = 0xFF000000;  in smsc_init()
401 	SMSC9220->RX_CFG = 0;  in smsc_init()
404 	/* Rx status FIFO level irq threshold */  in smsc_init()
405 	SMSC9220->FIFO_INT &= ~(0xFF);  /* Clear 2 bottom nibbles */  in smsc_init()
425 	struct eth_context *context = dev->data;  in get_stats()
427 	return &context->stats;  in get_stats()
434 	struct eth_context *context = dev->data;  in eth_initialize()
438 	smsc_read_mac_address(context->mac);  in eth_initialize()
440 	SMSC9220->INT_EN |= BIT(SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL);  in eth_initialize()
442 	net_if_set_link_addr(iface, context->mac, sizeof(context->mac),  in eth_initialize()
445 	context->iface = iface;  in eth_initialize()
463 		return -1;  in smsc_write_tx_fifo()
469 		SMSC9220->TX_DATA_PORT = *buf32++;  in smsc_write_tx_fifo()
470 	} while (--len);  in smsc_write_tx_fifo()
487 	SMSC9220->TX_DATA_PORT = txcmd_a;  in eth_tx()
488 	SMSC9220->TX_DATA_PORT = txcmd_b;  in eth_tx()
499 	tx_stat = SMSC9220->TX_STAT_PORT;  in eth_tx()
505 	LOG_ERR("Writing pkt to FIFO failed");  in eth_tx()
506 	return -1;  in eth_tx()
523 	/* When performing a fast-forward, there must be at least 4 DWORDs  in smsc_discard_pkt()
524 	 * of data in the RX data FIFO for the packet being discarded. For  in smsc_discard_pkt()
526 	 * read from the RX data FIFO and discarded using standard PIO read  in smsc_discard_pkt()
529 	SMSC9220->RX_DP_CTRL = RX_DP_CTRL_RX_FFWD;  in smsc_discard_pkt()
534 	while ((SMSC9220->RX_DP_CTRL & RX_DP_CTRL_RX_FFWD) != 0) {  in smsc_wait_discard_pkt()
547 		buf32 = SMSC9220->RX_DATA_PORT;  in smsc_read_rx_fifo()
550 			return -1;  in smsc_read_rx_fifo()
552 	} while (--len);  in smsc_read_rx_fifo()
560 	struct eth_context *context = dev->data;  in smsc_recv_pkt()
567 	rem_size -= 4U;  in smsc_recv_pkt()
569 	pkt = net_pkt_rx_alloc_with_buffer(context->iface, rem_size,  in smsc_recv_pkt()
585 		uint32_t __unused dummy = SMSC9220->RX_DATA_PORT;  in smsc_recv_pkt()
590 		net_pkt_update_length(pkt, net_pkt_get_len(pkt) -  in smsc_recv_pkt()
591 				      (4 - (pkt_size & 3)));  in smsc_recv_pkt()
599 	uint32_t int_status = SMSC9220->INT_STS;  in eth_smsc911x_isr()
600 	struct eth_context *context = dev->data;  in eth_smsc911x_isr()
603 		int_status, SMSC9220->INT_EN);  in eth_smsc911x_isr()
610 		val = SMSC9220->RX_FIFO_INF;  in eth_smsc911x_isr()
613 		LOG_DBG("in RX FIFO: pkts: %u, bytes: %u",  in eth_smsc911x_isr()
620 		 * pending for as long as there're packets in FIFO. And when  in eth_smsc911x_isr()
634 		rx_stat = SMSC9220->RX_STAT_PORT;  in eth_smsc911x_isr()
640 		LOG_DBG("out RX FIFO: pkts: %u, bytes: %u",  in eth_smsc911x_isr()
645 			int res = net_recv_data(context->iface, pkt);  in eth_smsc911x_isr()
656 	SMSC9220->INT_STS = int_status;  in eth_smsc911x_isr()
672 		return -ENODEV;  in eth_init()