63 	while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {  in smsc_mac_regread()
68 	return 0;  in smsc_mac_regread()
79 	while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) {  in smsc_mac_regwrite()
82 	return 0;  in smsc_mac_regwrite()
87 	uint32_t val = 0U;  in smsc_phy_regread()
88 	uint32_t phycmd = 0U;  in smsc_phy_regread()
91 	if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &val) < 0) {  in smsc_phy_regread()
96 		*data = 0U;  in smsc_phy_regread()
100 	phycmd = 0U;  in smsc_phy_regread()
102 	phycmd |= (regoffset & 0x1F) << 6;  in smsc_phy_regread()
110 	val = 0U;  in smsc_phy_regread()
117 	} while (time_out != 0U && (val & MAC_MII_ACC_MIIBZY));  in smsc_phy_regread()
119 	if (time_out == 0U) {  in smsc_phy_regread()
123 	if (smsc_mac_regread(SMSC9220_MAC_MII_DATA, data) < 0) {  in smsc_phy_regread()
127 	return 0;  in smsc_phy_regread()
132 	uint32_t val = 0U;  in smsc_phy_regwrite()
133 	uint32_t phycmd = 0U;  in smsc_phy_regwrite()
136 	if (smsc_mac_regread(SMSC9220_MAC_MII_ACC, &val) < 0) {  in smsc_phy_regwrite()
144 	if (smsc_mac_regwrite(SMSC9220_MAC_MII_DATA, data & 0xFFFF) < 0) {  in smsc_phy_regwrite()
149 	phycmd |= (regoffset & 0x1F) << 6;  in smsc_phy_regwrite()
153 	if (smsc_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd) < 0) {  in smsc_phy_regwrite()
163 	} while (time_out != 0U && (phycmd & MAC_MII_ACC_MIIBZY));  in smsc_phy_regwrite()
165 	if (time_out == 0U) {  in smsc_phy_regwrite()
169 	return 0;  in smsc_phy_regwrite()
178 	if (res < 0) {  in smsc_read_mac_address()
182 	mac[0] = (uint8_t)(tmp >> 0);  in smsc_read_mac_address()
188 	if (res < 0) {  in smsc_read_mac_address()
192 	mac[4] = (uint8_t)(tmp >> 0);  in smsc_read_mac_address()
195 	return 0;  in smsc_read_mac_address()
205 	if (((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {  in smsc_check_id()
209 	switch (((id >> 16) & 0xFFFF)) {  in smsc_check_id()
210 	case 0x9220: /* SMSC9220 on MPS2 */  in smsc_check_id()
211 	case 0x0118: /* SMS9118 as emulated by QEMU */  in smsc_check_id()
218 	return 0;  in smsc_check_id()
230 	} while (time_out != 0U && (SMSC9220->HW_CFG & HW_CFG_SRST));  in smsc_soft_reset()
232 	if (time_out == 0U) {  in smsc_soft_reset()
236 	return 0;  in smsc_soft_reset()
249 	SMSC9220->INT_EN = 0;  in smsc_init_irqs()
251 	SMSC9220->INT_STS = 0xFFFFFFFF;  in smsc_init_irqs()
254 	SMSC9220->IRQ_CFG = 0x22000111;  in smsc_init_irqs()
269 	return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||  in smsc_check_phy()
270 	    (phyid1 == 0x0 && phyid2 == 0x0));  in smsc_check_phy()
287 	return 0;  in smsc_reset_phy()
295 	uint32_t aneg_adv = 0U;  in smsc_advertise_caps()
298 	aneg_adv |= 0xDE0;  in smsc_advertise_caps()
306 	uint32_t bcr = 0U;  in smsc_establish_link()
307 	uint32_t hw_cfg = 0U;  in smsc_establish_link()
315 	hw_cfg &= 0xF0000;  in smsc_establish_link()
322 	SMSC9220->TX_CFG = 0x2 /*TX_CFG_TX_ON*/;  in smsc_enable_xmit()
327 	uint32_t mac_cr = 0U;  in smsc_enable_mac_xmit()
339 	uint32_t mac_cr = 0U;  in smsc_enable_mac_recv()
348 	unsigned int phyreset = 0U;  in smsc_init()
350 	if (smsc_check_id() < 0) {  in smsc_init()
354 	if (smsc_soft_reset() < 0) {  in smsc_init()
362 	SMSC9220->AFC_CFG = 0x006E3740;  in smsc_init()
367 	SMSC9220->GPIO_CFG = 0x70070000;  in smsc_init()
373 	if (smsc_check_phy() < 0) {  in smsc_init()
377 	if (smsc_reset_phy() < 0) {  in smsc_init()
397 	SMSC9220->FIFO_INT = 0xFF000000;  in smsc_init()
401 	SMSC9220->RX_CFG = 0;  in smsc_init()
405 	SMSC9220->FIFO_INT &= ~(0xFF);  /* Clear 2 bottom nibbles */  in smsc_init()
410 	return 0;  in smsc_init()
454 	__ASSERT_NO_MSG(((uintptr_t)buf & 3) == 0);  in smsc_write_tx_fifo()
461 	if ((len & 3) != 0U || len == 0U) {  in smsc_write_tx_fifo()
472 	return 0;  in smsc_write_tx_fifo()
495 	if (res < 0) {  in eth_tx()
502 	return 0;  in eth_tx()
534 	while ((SMSC9220->RX_DP_CTRL & RX_DP_CTRL_RX_FFWD) != 0) {  in smsc_wait_discard_pkt()
542 	__ASSERT_NO_MSG((len & 3) == 0U && len >= 4U);  in smsc_read_rx_fifo()
554 	return 0;  in smsc_read_rx_fifo()
570 					   AF_UNSPEC, 0, K_NO_WAIT);  in smsc_recv_pkt()
577 	if (smsc_read_rx_fifo(pkt, rem_size) < 0) {  in smsc_recv_pkt()
623 		if (pkt_pending == 0U) {  in eth_smsc911x_isr()
647 			if (res < 0) {  in eth_smsc911x_isr()
664 	IRQ_CONNECT(DT_INST_IRQN(0),  in eth_init()
665 		    DT_INST_IRQ(0, priority),  in eth_init()
666 		    eth_smsc911x_isr, DEVICE_DT_INST_GET(0), 0);  in eth_init()
670 	if (ret != 0) {  in eth_init()
675 	irq_enable(DT_INST_IRQN(0));  in eth_init()
682 ETH_NET_DEVICE_DT_INST_DEFINE(0,