2  * Copyright 2022-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
36 	EthTrcv_BaudRateType baudrate;  in nxp_s32_eth_configure_port()  local
42 	baudrate = PHY_TO_NETC_SPEED(speed);  in nxp_s32_eth_configure_port()
43 	status = Netc_EthSwt_Ip_SetPortSpeed(NETC_SWITCH_IDX, port_idx, baudrate);  in nxp_s32_eth_configure_port()
64 	const struct nxp_s32_eth_config *cfg = dev->config;  in phy_link_state_changed()
65 	const struct nxp_s32_eth_data *ctx = dev->data;  in phy_link_state_changed()
69 	if (state->is_up) {  in phy_link_state_changed()
71 		nxp_s32_eth_configure_port(cfg->port_idx, state->speed);  in phy_link_state_changed()
72 		net_eth_carrier_on(ctx->iface);  in phy_link_state_changed()
75 		net_eth_carrier_off(ctx->iface);  in phy_link_state_changed()
81 	const struct nxp_s32_eth_config *cfg = dev->config;  in nxp_s32_eth_get_phy()
83 	return cfg->phy_dev;  in nxp_s32_eth_get_phy()
92 		IP_MC_CGM_1->MUX_7_CSC = (IP_MC_CGM_1->MUX_7_CSC & ~MC_CGM_MUX_7_CSC_SELCTL_MASK)  in nxp_s32_eth_configure_cgm()
94 		IP_MC_CGM_1->MUX_7_CSC = (IP_MC_CGM_1->MUX_7_CSC & ~MC_CGM_MUX_7_CSC_CLK_SW_MASK)  in nxp_s32_eth_configure_cgm()
97 		while (((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_CLK_SW_MASK) == 0)  in nxp_s32_eth_configure_cgm()
99 			tout--;  in nxp_s32_eth_configure_cgm()
101 		while (((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SWIP_MASK) != 0)  in nxp_s32_eth_configure_cgm()
103 			tout--;  in nxp_s32_eth_configure_cgm()
105 		while (((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SWTRG_MASK)  in nxp_s32_eth_configure_cgm()
107 			tout--;  in nxp_s32_eth_configure_cgm()
110 		__ASSERT_NO_MSG(((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK)  in nxp_s32_eth_configure_cgm()
114 		IP_MC_CGM_1->MUX_9_CSC = (IP_MC_CGM_1->MUX_9_CSC & ~MC_CGM_MUX_9_CSC_SELCTL_MASK)  in nxp_s32_eth_configure_cgm()
116 		IP_MC_CGM_1->MUX_9_CSC = (IP_MC_CGM_1->MUX_9_CSC & ~MC_CGM_MUX_9_CSC_CLK_SW_MASK)  in nxp_s32_eth_configure_cgm()
119 		while (((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_CLK_SW_MASK) == 0)  in nxp_s32_eth_configure_cgm()
121 			tout--;  in nxp_s32_eth_configure_cgm()
123 		while (((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SWIP_MASK) != 0)  in nxp_s32_eth_configure_cgm()
125 			tout--;  in nxp_s32_eth_configure_cgm()
127 		while (((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SWTRG_MASK)  in nxp_s32_eth_configure_cgm()
129 			tout--;  in nxp_s32_eth_configure_cgm()
132 		__ASSERT_NO_MSG(((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)  in nxp_s32_eth_configure_cgm()
135 		return -EINVAL;  in nxp_s32_eth_configure_cgm()
143 	const struct nxp_s32_eth_config *cfg = dev->config;  in nxp_s32_eth_initialize()
146 	err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);  in nxp_s32_eth_initialize()
151 	err = nxp_s32_eth_configure_cgm(cfg->port_idx);  in nxp_s32_eth_initialize()
154 		return -EIO;  in nxp_s32_eth_initialize()
163 	struct nxp_s32_eth_data *ctx = dev->data;  in nxp_s32_eth_iface_init()
164 	const struct nxp_s32_eth_config *cfg = dev->config;  in nxp_s32_eth_iface_init()
172 	if (ctx->iface == NULL) {  in nxp_s32_eth_iface_init()
173 		ctx->iface = iface;  in nxp_s32_eth_iface_init()
176 	Netc_Eth_Ip_SetMacAddr(cfg->si_idx, (const uint8_t *)ctx->mac_addr);  in nxp_s32_eth_iface_init()
177 	net_if_set_link_addr(iface, ctx->mac_addr, sizeof(ctx->mac_addr), NET_LINK_ETHERNET);  in nxp_s32_eth_iface_init()
179 	LOG_INF("SI%d MAC: %02x:%02x:%02x:%02x:%02x:%02x", cfg->si_idx,  in nxp_s32_eth_iface_init()
180 		ctx->mac_addr[0], ctx->mac_addr[1], ctx->mac_addr[2],  in nxp_s32_eth_iface_init()
181 		ctx->mac_addr[3], ctx->mac_addr[4], ctx->mac_addr[5]);  in nxp_s32_eth_iface_init()
186 	 * PSI controls the PHY. If PHY is configured either as fixed  in nxp_s32_eth_iface_init()
190 	if (!device_is_ready(cfg->phy_dev)) {  in nxp_s32_eth_iface_init()
192 			cfg->phy_dev);  in nxp_s32_eth_iface_init()
195 	phy_link_callback_set(cfg->phy_dev, &phy_link_state_changed, (void *)dev);  in nxp_s32_eth_iface_init()
201 		msix = &cfg->msix[i];  in nxp_s32_eth_iface_init()
202 		if (mbox_is_ready_dt(&msix->mbox_spec)) {  in nxp_s32_eth_iface_init()
203 			if (mbox_set_enabled_dt(&msix->mbox_spec, true)) {  in nxp_s32_eth_iface_init()
205 					msix->mbox_spec.channel_id);  in nxp_s32_eth_iface_init()
244 	[DT_PROP_BY_IDX(node, prop, idx) - 1] =							\
274 	const struct nxp_s32_eth_config *cfg = dev->config;				\
275 	struct nxp_s32_eth_data *ctx = dev->data;					\
279 	if (ring == cfg->rx_ring_idx) {							\
280 		k_sem_give(&ctx->rx_sem);						\
450 		return -EIO;  in DT_INST_FOREACH_STATUS_OKAY()
460  * and ENETC, and initialize MDIO with a fixed configuration.