Lines Matching refs:uint32_t
25 uint32_t status; /*!< Status */
26 uint32_t control_buffer_size; /*!< Control and Buffer1, Buffer2 sizes */
27 uint32_t buffer1_addr; /*!< Buffer1 address pointer */
28 uint32_t buffer2_next_desc_addr; /*!< Buffer2 or next desc address pointer */
34 uint32_t interrupt_mask;
36 uint32_t tx_current_desc_number;
37 uint32_t rx_current_desc_number;
38 uint32_t tx_tail;
40 uint32_t feature; /* HW feature register */
43 uint32_t rxints; /* Tx stats */
44 uint32_t txints; /* Rx stats */
123 #define EMAC_DMAGRP_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMA_MODE_OFST) /* Bus Mode */
124 #define EMAC_DMA_RX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_DESC_LIST_OFST)
126 #define EMAC_DMA_TX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_DESC_LIST_OFST)
128 #define EMAC_DMAGRP_OPERATION_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_OPERATION_MODE_OFST)
130 #define EMAC_DMAGRP_STATUS_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_STATUS_OFST) /* Status */
131 #define EMAC_DMAGRP_DEBUG_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_DEBUG_OFST) /* Debug */
132 #define EMAC_DMA_INT_EN_ADDR(base) (uint32_t)((base) + EMAC_DMA_INT_EN_OFST)
134 #define EMAC_DMAGRP_AXI_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_AXI_BUS_MODE_OFST)
137 (uint32_t)((base) + EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST)
140 (uint32_t)((base) + \
143 #define EMAC_GMAC_INT_MSK_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_MSK_OFST)
145 #define EMAC_GMAC_INT_STAT_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_STAT_OFST)
147 #define GMACGRP_MAC_CONFIG_ADDR(base) (uint32_t)((base) + EMAC_GMACGRP_MAC_CONFIGURATION_OFST)
150 (uint32_t)((base) + EMAC_GMACGRP_MAC_FRAME_FILTER_OFST)
152 #define EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_HIGH_OFST)
154 #define EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_LOW_OFST)
156 #define EMAC_GMAC_MAC_ADDR_HIGH_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_HIGH_OFST(n))
158 #define EMAC_GMAC_MAC_ADDR_LOW_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_LOW_OFST(n))
160 #define EMAC_GMAC_GMII_ADDR_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_ADDR_OFST)
162 #define EMAC_GMAC_GMII_DATA_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_DATA_OFST)
164 #define EMAC_DMA_TX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_POLL_DEMAND_OFST)
166 #define EMAC_DMA_RX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_POLL_DEMAND_OFST)
168 #define EMAC_DMA_CURR_HOST_TX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_DESC_OFST)
170 #define EMAC_DMA_CURR_HOST_RX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_DESC_OFST)
172 #define EMAC_DMA_CURR_HOST_TX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_BUFF_OFST)
174 #define EMAC_DMA_CURR_HOST_RX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_BUFF_OFST)
176 #define EMAC_DMA_HW_FEATURE_ADDR(base) (uint32_t)((base) + EMAC_DMA_HW_FEATURE_OFST)
346 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
348 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
350 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
352 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
356 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
358 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
360 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
362 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
364 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
366 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
368 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
370 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
372 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
374 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
376 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
378 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
380 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
382 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
384 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
390 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
391 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
392 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
394 ((uint32_t)0x00004000) /*!< Second Address Chained \
396 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
416 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
418 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000)
420 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000)
422 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000)
424 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000)
426 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000)
428 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
430 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
432 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
434 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
436 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
438 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
440 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000)
442 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
444 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
446 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
448 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
451 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
453 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
455 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
457 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
459 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
461 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
463 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
465 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
467 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
469 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
471 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
473 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
478 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size \
481 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size \
485 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
488 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
491 static const uint32_t Rstmgr_Permodrst_Emac_Set_Msk[] = {RSTMGR_PERMODRST_EMAC0_SET_MSK,
494 static const uint32_t Sysmgr_Core_Emac_Phy_Intf_Sel_Set_Msk[] = {SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK,
497 static const uint32_t Sysmgr_Fpgaintf_En_3_Emac_Set_Msk[] = {SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK,
500 static const uint32_t Sysmgr_Emac_Phy_Intf_Sel_E_Rgmii[] = {SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII,