182 #define EMAC_DMA_MODE_SWR_GET(value)	   (((value)&0x00000001) >> 0)  argument
184 #define EMAC_DMA_MODE_RPBL_SET(value)	   (((value) << 17) & 0x007e0000)  argument
185 #define EMAC_DMA_MODE_PBL_SET(value)	   (((value) << 8) & 0x00003f00)  argument
186 #define EMAC_DMA_MODE_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000)  argument
234 #define EMAC_DMAGRP_DEBUG_RXFSTS_GET(value) (((value)&0x00000300) >> 8)  argument
261 #define EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value)	  (((value)&0x00000008) >> 3)  argument
262 #define EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value)	  (((value)&0x00000007) >> 1)  argument
263 #define EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value)	  ((value)&0x00000001)  argument
287 #define EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800)  argument
288 #define EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0)  argument
291 #define EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c)  argument
292 #define EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001)  argument