Lines Matching +full:promiscuous +full:- +full:mode
2 * SPDX-License-Identifier: Apache-2.0
5 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
9 * https://github.com/altera-opensource/intel-socfpga-hwlib
71 * /us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p. 1252
135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
156 return -1; in eth_cyclonev_get_software_reset_status()
158 return EMAC_DMA_MODE_SWR_GET(sys_read32(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr))); in eth_cyclonev_get_software_reset_status()
167 * @retval 0 if Reset was successful, -1 otherwise
175 return -1; in eth_cyclonev_software_reset()
180 sys_set_bits(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr), EMAC_DMA_MODE_SWR_SET_MSK); in eth_cyclonev_software_reset()
191 return -1; in eth_cyclonev_software_reset()
212 rx_desc = &p->rx_desc_ring[i]; in eth_cyclonev_setup_rxdesc()
213 rx_desc->buffer1_addr = (uint32_t)&p->rx_buf[i * ETH_BUFFER_SIZE]; in eth_cyclonev_setup_rxdesc()
214 rx_desc->control_buffer_size = ETH_DMARXDESC_RCH | ETH_BUFFER_SIZE; in eth_cyclonev_setup_rxdesc()
217 rx_desc->status = ETH_DMARXDESC_OWN; in eth_cyclonev_setup_rxdesc()
219 rx_desc->buffer2_next_desc_addr = (uint32_t)&p->rx_desc_ring[i + 1]; in eth_cyclonev_setup_rxdesc()
220 if (i == (NB_RX_DESCS - 1)) { in eth_cyclonev_setup_rxdesc()
221 rx_desc->buffer2_next_desc_addr = (uint32_t)&p->rx_desc_ring[0]; in eth_cyclonev_setup_rxdesc()
225 p->rx_current_desc_number = 0; in eth_cyclonev_setup_rxdesc()
226 p->rxints = 0; in eth_cyclonev_setup_rxdesc()
229 sys_write32((uint32_t)&p->rx_desc_ring[0], in eth_cyclonev_setup_rxdesc()
230 EMAC_DMA_RX_DESC_LIST_ADDR(p->base_addr)); in eth_cyclonev_setup_rxdesc()
249 tx_desc = &p->tx_desc_ring[i]; in eth_cyclonev_setup_txdesc()
250 tx_desc->buffer1_addr = (uint32_t)&p->tx_buf[i * ETH_BUFFER_SIZE]; in eth_cyclonev_setup_txdesc()
251 tx_desc->buffer2_next_desc_addr = (uint32_t)&p->tx_desc_ring[i + 1]; in eth_cyclonev_setup_txdesc()
252 tx_desc->status = 0; in eth_cyclonev_setup_txdesc()
253 tx_desc->control_buffer_size = 0; in eth_cyclonev_setup_txdesc()
255 if (i == (NB_TX_DESCS - 1)) { in eth_cyclonev_setup_txdesc()
256 tx_desc->buffer2_next_desc_addr = (uint32_t)&p->tx_desc_ring[0]; in eth_cyclonev_setup_txdesc()
260 p->tx_current_desc_number = 0; in eth_cyclonev_setup_txdesc()
261 p->txints = 0; in eth_cyclonev_setup_txdesc()
262 p->tx_tail = 0; in eth_cyclonev_setup_txdesc()
265 sys_write32((uint32_t)&p->tx_desc_ring[0], in eth_cyclonev_setup_txdesc()
266 EMAC_DMA_TX_DESC_LIST_ADDR(p->base_addr)); in eth_cyclonev_setup_txdesc()
280 const struct eth_cyclonev_config *config = dev->config; in eth_cyclonev_iface_init()
281 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_iface_init()
283 p->iface = iface; in eth_cyclonev_iface_init()
285 net_if_set_link_addr(iface, p->mac_addr, sizeof(p->mac_addr), NET_LINK_ETHERNET); in eth_cyclonev_iface_init()
294 k_sem_init(&p->free_tx_descs, NB_TX_DESCS - 1, NB_TX_DESCS - 1); in eth_cyclonev_iface_init()
297 config->irq_config(); in eth_cyclonev_iface_init()
299 p->initialised = 1; in eth_cyclonev_iface_init()
306 * Set of Mac address and Enabling Promiscuous Mode
317 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_set_config()
318 const struct eth_cyclonev_config *cv_config = dev->config; in eth_cyclonev_set_config()
326 memcpy(p->mac_addr, config->mac_address.addr, sizeof(p->mac_addr)); in eth_cyclonev_set_config()
327 eth_cyclonev_set_mac_addr(p->mac_addr, cv_config->emac_index, 0, p); /* Set MAC */ in eth_cyclonev_set_config()
328 net_if_set_link_addr(p->iface, p->mac_addr, sizeof(p->mac_addr), NET_LINK_ETHERNET); in eth_cyclonev_set_config()
332 reg_val = sys_read32(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr)); in eth_cyclonev_set_config()
333 if (config->promisc_mode && !(reg_val & EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK)) { in eth_cyclonev_set_config()
334 /* Turn on Promisc Mode */ in eth_cyclonev_set_config()
335 sys_set_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
337 } else if (!config->promisc_mode && in eth_cyclonev_set_config()
339 /* Turn off Promisc Mode */ in eth_cyclonev_set_config()
340 sys_clear_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
343 ret = -EALREADY; in eth_cyclonev_set_config()
348 ret = -ENOTSUP; in eth_cyclonev_set_config()
365 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_caps()
368 if (p->feature & EMAC_DMA_HW_FEATURE_MIISEL) { in eth_cyclonev_caps()
372 if (p->feature & EMAC_DMA_HW_FEATURE_GMIISEL) { in eth_cyclonev_caps()
375 if (p->feature & EMAC_DMA_HW_FEATURE_RXTYP2COE) { in eth_cyclonev_caps()
378 if (p->feature & EMAC_DMA_HW_FEATURE_RXTYP1COE) { in eth_cyclonev_caps()
391 * literature/hb/cyclone-v/cv_54001.pdf p.1254 and p.1206
395 * @retval 0 if successful, -1 otherwise
402 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_send()
410 frag = pkt->buffer; in eth_cyclonev_send()
414 if (k_sem_take(&p->free_tx_descs, TX_AVAIL_WAIT) != 0) { in eth_cyclonev_send()
419 tx_desc = &p->tx_desc_ring[p->tx_current_desc_number]; in eth_cyclonev_send()
422 if (tx_desc->status & ETH_DMATXDESC_OWN) { in eth_cyclonev_send()
437 memcpy(&p->tx_buf[p->tx_current_desc_number * ETH_BUFFER_SIZE], frag->data, in eth_cyclonev_send()
442 tx_desc->control_buffer_size = (frag->len & ETH_DMATXDESC_TBS1); in eth_cyclonev_send()
445 p->tx_current_desc_number, in eth_cyclonev_send()
446 (unsigned int)&p->tx_desc_ring[p->tx_current_desc_number], frag->len, in eth_cyclonev_send()
447 (void *)tx_desc->buffer1_addr); in eth_cyclonev_send()
449 tx_desc->status = ETH_DMATXDESC_TCH; in eth_cyclonev_send()
453 tx_desc->status |= (ETH_DMATXDESC_FS | ETH_DMATXDESC_CIC_BYPASS); in eth_cyclonev_send()
458 if (!frag->frags) { in eth_cyclonev_send()
460 tx_desc->status |= (ETH_DMATXDESC_LS | ETH_DMATXDESC_IC); in eth_cyclonev_send()
461 index = p->tx_current_desc_number; in eth_cyclonev_send()
465 p->tx_current_desc_number = (p->tx_current_desc_number + 1); in eth_cyclonev_send()
466 if (p->tx_current_desc_number >= NB_TX_DESCS) { in eth_cyclonev_send()
467 p->tx_current_desc_number = 0; in eth_cyclonev_send()
470 if (!frag->frags) { in eth_cyclonev_send()
474 tx_desc = &p->tx_desc_ring[index]; in eth_cyclonev_send()
476 if (tx_desc->status & ETH_DMATXDESC_OWN) { in eth_cyclonev_send()
478 /* Restart DMA transmission and re-initialise in eth_cyclonev_send()
482 p->base_addr), in eth_cyclonev_send()
485 p->base_addr), in eth_cyclonev_send()
489 p->base_addr), in eth_cyclonev_send()
495 tx_desc->status |= ETH_DMATXDESC_OWN; in eth_cyclonev_send()
497 if (tx_desc->status & ETH_DMATXDESC_FS) { in eth_cyclonev_send()
501 index--; in eth_cyclonev_send()
503 index = NB_TX_DESCS - 1; in eth_cyclonev_send()
509 EMAC_DMA_CURR_HOST_TX_DESC_ADDR(p->base_addr))); in eth_cyclonev_send()
512 EMAC_DMA_CURR_HOST_TX_BUFF_ADDR(p->base_addr))); in eth_cyclonev_send()
515 if (sys_read32(EMAC_DMAGRP_STATUS_ADDR(p->base_addr)) & in eth_cyclonev_send()
520 EMAC_DMAGRP_STATUS_ADDR(p->base_addr)); in eth_cyclonev_send()
524 EMAC_DMA_TX_POLL_DEMAND_ADDR(p->base_addr)); in eth_cyclonev_send()
527 frag = frag->frags; in eth_cyclonev_send()
534 k_sem_give(&p->free_tx_descs); /* Multi-descriptor package release (?) */ in eth_cyclonev_send()
536 return -1; in eth_cyclonev_send()
549 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_isr()
550 const struct eth_cyclonev_config *config = dev->config; in eth_cyclonev_isr()
555 sys_read32(EMAC_DMAGRP_STATUS_ADDR(p->base_addr)) & p->interrupt_mask; in eth_cyclonev_isr()
556 irq_status_emac = sys_read32(EMAC_GMAC_INT_STAT_ADDR(p->base_addr)); in eth_cyclonev_isr()
561 EMAC_DMAGRP_STATUS_ADDR(p->base_addr)); in eth_cyclonev_isr()
565 p->txints++; in eth_cyclonev_isr()
569 EMAC_DMAGRP_STATUS_ADDR(p->base_addr)); in eth_cyclonev_isr()
573 p->rxints++; in eth_cyclonev_isr()
577 EMAC_DMAGRP_STATUS_ADDR(p->base_addr)); in eth_cyclonev_isr()
582 uint32_t regval = sys_read32(GMACGRP_CONTROL_STATUS_ADDR(p->base_addr)); in eth_cyclonev_isr()
612 if (p->initialised) { in eth_cyclonev_isr()
615 cfg_reg_set = sys_read32(GMACGRP_MAC_CONFIG_ADDR(p->base_addr)); in eth_cyclonev_isr()
617 if (eth_cyclonev_stop(dev) == -1) { in eth_cyclonev_isr()
618 LOG_ERR("Couldn't stop device: %s", dev->name); in eth_cyclonev_isr()
622 set_mac_conf_status(config->emac_index, &cfg_reg_set, p); in eth_cyclonev_isr()
623 sys_write32(cfg_reg_set, GMACGRP_MAC_CONFIG_ADDR(p->base_addr)); in eth_cyclonev_isr()
646 index = p->rx_current_desc_number; in eth_cyclonev_receive()
647 rx_desc = &p->rx_desc_ring[index]; in eth_cyclonev_receive()
649 while (!(rx_desc->status & ETH_DMARXDESC_OWN)) { in eth_cyclonev_receive()
651 LOG_DBG("RDES0[%d] = 0x%08x", index, rx_desc->status); in eth_cyclonev_receive()
653 if (!(rx_desc->status & ETH_DMARXDESC_FS)) { in eth_cyclonev_receive()
655 rx_desc->status |= ETH_DMARXDESC_OWN; in eth_cyclonev_receive()
664 rx_desc = &p->rx_desc_ring[rx_search]; in eth_cyclonev_receive()
666 frame_length = data_remaining = (ETH_DMARXDESC_FL & rx_desc->status) >> 16; in eth_cyclonev_receive()
668 if (!(rx_desc->status & ETH_DMARXDESC_LS)) { in eth_cyclonev_receive()
672 rx_desc = &p->rx_desc_ring[index]; in eth_cyclonev_receive()
673 rx_desc->status |= ETH_DMARXDESC_OWN; in eth_cyclonev_receive()
677 } while (!(rx_desc->status & ETH_DMARXDESC_LS)); in eth_cyclonev_receive()
680 p->rx_current_desc_number = last_desc_index; in eth_cyclonev_receive()
683 pkt = net_pkt_rx_alloc_with_buffer(p->iface, frame_length, AF_UNSPEC, 0, K_NO_WAIT); in eth_cyclonev_receive()
686 eth_stats_update_errors_rx(p->iface); in eth_cyclonev_receive()
693 rx_desc = &p->rx_desc_ring[rx_search]; in eth_cyclonev_receive()
700 net_pkt_write(pkt, &p->rx_buf[rx_search * ETH_BUFFER_SIZE], in eth_cyclonev_receive()
703 data_remaining -= buf_size; in eth_cyclonev_receive()
704 rx_desc->status |= ETH_DMARXDESC_OWN; in eth_cyclonev_receive()
714 rx_desc = &p->rx_desc_ring[rx_search]; in eth_cyclonev_receive()
723 &p->rx_buf[rx_search * ETH_BUFFER_SIZE], in eth_cyclonev_receive()
726 data_remaining -= buf_size; in eth_cyclonev_receive()
728 rx_desc->status |= ETH_DMARXDESC_OWN; in eth_cyclonev_receive()
733 /* Hand-over packet into IP stack */ in eth_cyclonev_receive()
735 if (net_recv_data(p->iface, pkt) < 0) { in eth_cyclonev_receive()
736 LOG_ERR("RX packet hand-over to IP stack failed"); in eth_cyclonev_receive()
743 p->rx_current_desc_number++; in eth_cyclonev_receive()
744 if (p->rx_current_desc_number == NB_RX_DESCS) { in eth_cyclonev_receive()
745 p->rx_current_desc_number = 0; in eth_cyclonev_receive()
747 index = p->rx_current_desc_number; in eth_cyclonev_receive()
748 rx_desc = &p->rx_desc_ring[index]; in eth_cyclonev_receive()
766 for (d_idx = p->tx_tail; d_idx != p->tx_current_desc_number; in eth_cyclonev_tx_release()
767 INC_WRAP(d_idx, NB_TX_DESCS), k_sem_give(&p->free_tx_descs)) { in eth_cyclonev_tx_release()
769 d = &p->tx_desc_ring[d_idx]; in eth_cyclonev_tx_release()
770 des3_val = d->status; in eth_cyclonev_tx_release()
783 eth_stats_update_errors_tx(p->iface); in eth_cyclonev_tx_release()
787 p->tx_tail = d_idx; in eth_cyclonev_tx_release()
792 * Detects PHY Mode and assigns MAC Config Register
796 * @retval updated mac_config_reg mask (>=0), -1 otherwise
798 /* Configure the MAC with the speed fixed by the auto-negotiation process */
811 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ in set_mac_conf_status()
815 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ in set_mac_conf_status()
820 /* Set Ethernet speed to 10M following the auto-negotiation */ in set_mac_conf_status()
826 /* Set Ethernet speed to 100M following the auto-negotiation */ in set_mac_conf_status()
832 /* Set Ethernet speed to 1G following the auto-negotiation */ in set_mac_conf_status()
845 * www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p.1252-54
848 * @retval 0 if successful, -1 otherwise
853 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_probe()
854 const struct eth_cyclonev_config *config = dev->config; in eth_cyclonev_probe()
859 p->base_addr = (mem_addr_t)config->base; in eth_cyclonev_probe()
860 p->running = 0; in eth_cyclonev_probe()
861 p->initialised = 0; in eth_cyclonev_probe()
866 eth_cyclonev_reset(config->emac_index); in eth_cyclonev_probe()
869 ret = alt_eth_phy_reset(config->emac_index, p); in eth_cyclonev_probe()
876 ret = alt_eth_phy_config(config->emac_index, p); in eth_cyclonev_probe()
884 p->feature = sys_read32(EMAC_DMA_HW_FEATURE_ADDR(p->base_addr)); in eth_cyclonev_probe()
891 *Register 0 (Bus Mode Register), which is only cleared after the reset in eth_cyclonev_probe()
895 ret = eth_cyclonev_software_reset(config->emac_index, p); in eth_cyclonev_probe()
901 /* 4. Program the following fields to initialize the Bus Mode Register by in eth_cyclonev_probe()
902 * setting values in DMA Register 0 (Bus Mode Register): in eth_cyclonev_probe()
907 EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr)); in eth_cyclonev_probe()
909 /* 5. Program the interface options in Register 10 (AXI Bus Mode in eth_cyclonev_probe()
910 * Register). If fixed burst-length is enabled, then select the maximum in eth_cyclonev_probe()
911 * burst-length possible on the bus (bits[7:1]).(58) in eth_cyclonev_probe()
914 tmpreg = sys_read32(EMAC_DMAGRP_AXI_BUS_MODE_ADDR(p->base_addr)); in eth_cyclonev_probe()
918 EMAC_DMAGRP_AXI_BUS_MODE_ADDR(p->base_addr)); /* Set Burst Length = 16 */ in eth_cyclonev_probe()
934 /* 9. Program the following fields to initialize the mode of operation in in eth_cyclonev_probe()
935 * Register 6 (Operation Mode Register): in eth_cyclonev_probe()
942 EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr)); in eth_cyclonev_probe()
953 p->interrupt_mask = interrupt_mask; in eth_cyclonev_probe()
956 sys_write32(interrupt_mask, EMAC_DMAGRP_STATUS_ADDR(p->base_addr)); in eth_cyclonev_probe()
962 sys_set_bits(EMAC_DMA_INT_EN_ADDR(p->base_addr), interrupt_mask); in eth_cyclonev_probe()
968 if (sys_read32(EMAC_DMAGRP_AHB_OR_AXI_STATUS_ADDR(p->base_addr)) != 0) { in eth_cyclonev_probe()
970 return -1; in eth_cyclonev_probe()
980 * 2. Read the 16-bit data of the GMII Data Register from the PHY for link up, in eth_cyclonev_probe()
981 * speed of operation, and mode of operation, by specifying the appropriate in eth_cyclonev_probe()
997 ret = set_mac_conf_status(config->emac_index, &mac_config_reg_settings, p); in eth_cyclonev_probe()
999 return -1; in eth_cyclonev_probe()
1007 memcpy(p->mac_addr, eth_cyclonev_mac_addr, sizeof(p->mac_addr)); in eth_cyclonev_probe()
1008 eth_cyclonev_set_mac_addr(p->mac_addr, config->emac_index, 0, p); in eth_cyclonev_probe()
1013 * • Promiscuous mode in eth_cyclonev_probe()
1018 sys_clear_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_probe()
1019 EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK); /* Disable promiscuous mode */ in eth_cyclonev_probe()
1025 sys_set_bits(EMAC_GMAC_INT_MSK_ADDR(p->base_addr), in eth_cyclonev_probe()
1033 sys_write32(mac_config_reg_settings, GMACGRP_MAC_CONFIG_ADDR(p->base_addr)); in eth_cyclonev_probe()
1043 * www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p.1255-56
1052 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_start()
1054 if (p->running) { in eth_cyclonev_start()
1059 /*6. To re-start the operation, first start the DMA and then enable in eth_cyclonev_start()
1064 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1066 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1070 sys_set_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_start()
1072 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1074 sys_set_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_start()
1077 p->running = 1; in eth_cyclonev_start()
1086 * programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p.1255-56
1089 * @retval 0 if successful, -1 otherwise
1095 struct eth_cyclonev_priv *p = dev->data; in eth_cyclonev_stop()
1097 if (!p->running) { in eth_cyclonev_stop()
1102 * (Start or Stop Transmission Command) of Register 6 (Operation Mode in eth_cyclonev_stop()
1106 sys_clear_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_stop()
1112 sys_clear_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_stop()
1114 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_stop()
1116 sys_clear_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_stop()
1124 sys_clear_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_stop()
1130 sys_read32(EMAC_DMAGRP_DEBUG_ADDR(p->base_addr))) != 0x0) { in eth_cyclonev_stop()
1131 return -1; in eth_cyclonev_stop()
1134 p->running = 0; in eth_cyclonev_stop()