39 #define MTL_RXQ_DMA_MAP_QxDDMACH_SET(q_pos, value) ((value & 0x1u) << (8u * q_pos + 7u))  argument
40 #define MTL_RXQ_DMA_MAP_QxMDMACH_SET(q_pos, value) ((value & 0x7u) << (8u * q_pos))  argument
50 #define DMA_MODE_SWR_SET(value) ((value) & 0x00000001)  argument
56 #define DMA_MODE_INTM_SET(value) (((value) << 12) & 0x00003000)  argument
60 #define DMA_SYSBUS_MODE_RD_OSR_LMT_SET(value) (((value) << 16) & 0x001f0000)  argument
62 #define DMA_SYSBUS_MODE_WR_OSR_LMT_SET(value) (((value) << 24) & 0x1f000000)  argument
64 #define DMA_SYSBUS_MODE_AAL_SET(value) (((value) << 12) & 0x00001000)  argument
66 #define DMA_SYSBUS_MODE_EAME_SET(value) (((value) << 11) & 0x00000800)  argument
68 #define DMA_SYSBUS_MODE_BLEN4_SET(value) (((value) << 1) & 0x00000002)  argument
70 #define DMA_SYSBUS_MODE_BLEN8_SET(value) (((value) << 2) & 0x00000004)  argument
72 #define DMA_SYSBUS_MODE_BLEN16_SET(value) (((value) << 3) & 0x00000008)  argument
74 #define DMA_SYSBUS_MODE_BLEN32_SET(value) (((value) << 4) & 0x00000010)  argument
76 #define DMA_SYSBUS_MODE_BLEN64_SET(value) (((value) << 5) & 0x00000020)  argument
78 #define DMA_SYSBUS_MODE_BLEN128_SET(value) (((value) << 6) & 0x00000040)  argument
80 #define DMA_SYSBUS_MODE_BLEN256_SET(value) (((value) << 7) & 0x00000080)  argument
82 #define DMA_SYSBUS_MODE_UNDEF_SET(value) ((value) & 0x00000001)  argument
86 #define DMA_TX_EDMA_CONTROL_TDPS_SET(value) ((value) & 0x00000003)  argument
90 #define DMA_RX_EDMA_CONTROL_RDPS_SET(value) ((value) & 0x00000003)  argument
120 #define DMA_CHx_CONTROL_SPH_SET(value) (((value) << 24) & 0x01000000)  argument
122 #define DMA_CHx_CONTROL_PBLX8_SET(value) (((value) << 16) & 0x00010000)  argument
124 #define DMA_CHx_CONTROL_MSS_SET(value) ((value) & 0x00003fff)  argument
128 #define DMA_CHx_TX_CONTROL_TXPBL_SET(value) (((value) << 16) & 0x003f0000)  argument
130 #define DMA_CHx_TX_CONTROL_TSE_SET(value) (((value) << 12) & 0x00001000)  argument
132 #define DMA_CHx_TX_CONTROL_RESERVED_OSP_SET(value) (((value) << 4) & 0x00000010)  argument
138 #define DMA_CHx_RX_CONTROL_RPF_SET(value) (((value) << 31) & 0x80000000)  argument
140 #define DMA_CHx_RX_CONTROL_RXPBL_SET(value) (((value) << 16) & 0x003f0000)  argument
142 #define DMA_CHx_RX_CONTROL_RBSZ_SET(value) ((value << 1) & 0x00007ff0)  argument
148 #define DMA_CHx_TXDESC_LIST_HADDRESS_TDESHA_SET(value) ((value) & 0x000000ff)  argument
158 #define DMA_CHx_TXDESC_TAIL_LPOINTER_TDT_SET(value) ((value) & 0xfffffff8)  argument
162 #define DMA_CHx_RXDESC_TAIL_LPOINTER_RDT_SET(value) ((value) & 0xfffffff8)  argument
166 #define DMA_CHx_TX_CONTROL2_TDRL_SET(value) (((value) << 0) & 0x0000ffff)  argument
170 #define DMA_CHx_RX_CONTROL2_RDRL_SET(value) (((value) << 0) & 0x0000ffff)  argument
178 #define DMA_CHx_INTERRUPT_ENABLE_NIE_SET(value) (((value) << 15) & 0x00008000)  argument
180 #define DMA_CHx_INTERRUPT_ENABLE_AIE_SET(value) (((value) << 14) & 0x00004000)  argument
182 #define DMA_CHx_INTERRUPT_ENABLE_CDEE_SET(value) (((value) << 13) & 0x00002000)  argument
184 #define DMA_CHx_INTERRUPT_ENABLE_FBEE_SET(value) (((value) << 12) & 0x00001000)  argument
186 #define DMA_CHx_INTERRUPT_ENABLE_DDEE_SET(value) (((value) << 9) & 0x00000200)  argument
188 #define DMA_CHx_INTERRUPT_ENABLE_RSE_SET(value) (((value) << 8) & 0x00000100)  argument
190 #define DMA_CHx_INTERRUPT_ENABLE_RBUE_SET(value) (((value) << 7) & 0x00000080)  argument
192 #define DMA_CHx_INTERRUPT_ENABLE_RIE_SET(value) (((value) << 6) & 0x00000040)  argument
194 #define DMA_CHx_INTERRUPT_ENABLE_TBUE_SET(value) (((value) << 2) & 0x00000004)  argument
196 #define DMA_CHx_INTERRUPT_ENABLE_TXSE_SET(value) (((value) << 1) & 0x00000002)  argument
198 #define DMA_CHx_INTERRUPT_ENABLE_TIE_SET(value) (((value) << 0) & 0x00000001)  argument
202 #define MTL_OPERATION_MODE_ETSALG_SET(value) (((value) << 5) & 0x00000060)  argument
204 #define MTL_OPERATION_MODE_RAA_SET(value) (((value) << 2) & 0x00000004)  argument
212 #define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TQS_SET(value) (((value) << 16) & 0x007f0000)  argument
214 #define MTL_TCQx_MTL_TXQx_OPERATION_MODE_Q2TCMAP_SET(value) (((value) << 8) & 0x00000700)  argument
216 #define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TTC_SET(value) (((value) << 4) & 0x00000070)  argument
218 #define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TXQEN_SET(value) (((value) << 2) & 0x0000000c)  argument
220 #define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TSF_SET(value) (((value) << 1) & 0x00000002)  argument
224 #define MTL_TCQx_MTC_TCx_ETS_CONTROL_TSA_SET(value) (((value) << 0) & 0x00000003)  argument
228 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RQS_SET(value) (((value) << 16) & 0x003f0000)  argument
230 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_EHFC_SET(value) (((value) << 7) & 0x00000080)  argument
232 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_DIS_TCP_EF_SET(value) (((value) << 6) & 0x00000040)  argument
234 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RSF_SET(value) (((value) << 5) & 0x00000020)  argument
236 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_FEF_SET(value) (((value) << 4) & 0x00000010)  argument
238 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_FUF_SET(value) (((value) << 3) & 0x00000008)  argument
240 #define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RTC_SET(value) (((value) << 0) & 0x00000003)  argument
244 #define CORE_MAC_ADDRESSx_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)  argument
256 #define CORE_MAC_TX_CONFIGURATION_SS_SET(value) (((value) << 29) & 0xe0000000)  argument
258 #define CORE_MAC_TX_CONFIGURATION_JD_SET(value) (((value) << 16) & 0x00010000)  argument
264 #define CORE_MAC_RX_CONFIGURATION_GPSLCE_SET(value) (((value) << 6) & 0x00000040)  argument
266 #define CORE_MAC_RX_CONFIGURATION_WD_SET(value) (((value) << 7) & 0x00000080)  argument
268 #define CORE_MAC_RX_CONFIGURATION_JE_SET(value) (((value) << 8) & 0x00000100)  argument
270 #define CORE_MAC_RX_CONFIGURATION_ARPEN_SET(value) (((value) << 31) & 0x80000000)  argument
272 #define CORE_MAC_RX_CONFIGURATION_GPSL_SET(value) (((value) << 16) & 0x3fff0000)  argument
274 #define CORE_MAC_TX_CONFIGURATION_TE_SET(value) (((value) << 0) & 0x00000001)  argument
276 #define CORE_MAC_RX_CONFIGURATION_RE_SET(value) (((value) << 0) & 0x00000001)  argument
294 #define CORE_MAC_INTERRUPT_ENABLE_LSIE_SET(value) (((value) << 0) & 0x00000001)  argument
298 #define CORE_MAC_PACKET_FILTER_IPFE_SET(value) (((value) << 20) & 0x00100000)  argument
300 #define CORE_MAC_PACKET_FILTER_HPF_SET(value) (((value) << 10) & 0x00000400)  argument
302 #define CORE_MAC_PACKET_FILTER_HMC_SET(value) (((value) << 2) & 0x00000004)  argument
304 #define CORE_MAC_PACKET_FILTER_HUC_SET(value) (((value) << 1) & 0x00000002)  argument
306 #define CORE_MAC_RX_CONFIGURATION_IPC_SET(value) (((value) << 9) & 0x00000200)  argument
314 #define CORE_MAC_PACKET_FILTER_PR_SET(value) (((value) << 0) & 0x00000001)  argument
316 #define CORE_MAC_PACKET_FILTER_RA_SET(value) (((value) << 31) & 0x80000000)  argument
318 #define CORE_MAC_PACKET_FILTER_PM_SET(value) (((value) << 4) & 0x00000010)  argument
519 	 * programmed to a non-zero value (when split header feature is not enabled).
533 	/* When this is set, the PBL value programmed in Tx_control is multiplied
659 	 * DMA interrupt status value
667 	 * MTL interrupt status register value
671 	 * MAC interrupt status register value