Lines Matching refs:reg_addr
154 mem_addr_t reg_addr = in dwxgmac_dma_init() local
174 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
177 reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_TX_EDMA_CONTROL_OFST; in dwxgmac_dma_init()
181 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
184 reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_RX_EDMA_CONTROL_OFST; in dwxgmac_dma_init()
188 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
204 mem_addr_t reg_addr; in dwxgmac_dma_chnl_init() local
214 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
219 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
225 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
230 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
236 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
241 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
244 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
248 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
251 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
254 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
257 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
260 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
263 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
266 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
269 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
272 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
275 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
278 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
281 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
284 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
287 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in dwxgmac_dma_chnl_init()
290 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
344 mem_addr_t reg_addr = in dwxgmac_dma_mtl_init() local
348 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
352 reg_addr = (ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_TC_PRTY_MAP0_OFST + in dwxgmac_dma_mtl_init()
354 reg_val = (sys_read32(reg_addr) & in dwxgmac_dma_mtl_init()
358 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
370 reg_addr = (ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_RXQ_DMA_MAP0_OFST + in dwxgmac_dma_mtl_init()
372 reg_val = (sys_read32(reg_addr) & in dwxgmac_dma_mtl_init()
378 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
380 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
389 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
391 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
394 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
396 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
410 sys_write32(reg_val, reg_addr); in dwxgmac_dma_mtl_init()
527 mem_addr_t reg_addr; in dwxgmac_irq_init() local
531 reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_MODE_OFST; in dwxgmac_irq_init()
532 reg_val = (sys_read32(reg_addr) & DMA_MODE_INTM_CLR_MSK); in dwxgmac_irq_init()
533 sys_write32(reg_val, reg_addr); in dwxgmac_irq_init()
880 mem_addr_t reg_addr; in eth_dwc_xgmac_isr() local
912 reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_INTERRUPT_STATUS_OFST; in eth_dwc_xgmac_isr()
917 cntxt_data->dma_interrupt_sts |= sys_read32(reg_addr); in eth_dwc_xgmac_isr()
920 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) + in eth_dwc_xgmac_isr()
922 dmach_interrupt_sts = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
923 sys_write32(dmach_interrupt_sts, reg_addr); in eth_dwc_xgmac_isr()
938 reg_addr = ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_INTERRUPT_STATUS_OFST; in eth_dwc_xgmac_isr()
939 reg_val = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
946 reg_addr = ioaddr + XGMAC_CORE_BASE_ADDR_OFFSET + CORE_MAC_INTERRUPT_STATUS_OFST; in eth_dwc_xgmac_isr()
947 reg_val = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
1077 mem_addr_t reg_addr; in eth_dwc_xgmac_prefill_rx_desc() local
1133 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_prefill_rx_desc()
1136 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_prefill_rx_desc()
1199 mem_addr_t reg_addr; in eth_dwc_xgmac_start_device() local
1211 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_start_device()
1213 reg_val = sys_read32(reg_addr) | DMA_CHx_TX_CONTROL_ST_SET_MSK; in eth_dwc_xgmac_start_device()
1214 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_start_device()
1216 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_start_device()
1218 reg_val = sys_read32(reg_addr) | DMA_CHx_RX_CONTROL_SR_SET_MSK; in eth_dwc_xgmac_start_device()
1219 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_start_device()
1221 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_start_device()
1234 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_start_device()
1277 mem_addr_t reg_addr; in eth_dwc_xgmac_stop_device() local
1290 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_stop_device()
1292 reg_val = sys_read32(reg_addr) & DMA_CHx_TX_CONTROL_ST_CLR_MSK; in eth_dwc_xgmac_stop_device()
1293 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_stop_device()
1295 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_stop_device()
1297 reg_val = sys_read32(reg_addr) & DMA_CHx_RX_CONTROL_SR_CLR_MSK; in eth_dwc_xgmac_stop_device()
1298 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_stop_device()
1300 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in eth_dwc_xgmac_stop_device()
1303 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_stop_device()
1315 reg_addr = ioaddr + CORE_MAC_INTERRUPT_ENABLE_OFST; in eth_dwc_xgmac_stop_device()
1317 sys_write32(reg_val, reg_addr); in eth_dwc_xgmac_stop_device()
1333 mem_addr_t reg_addr, ioaddr = get_reg_base_addr(dev); in update_desc_tail_ptr() local
1336 reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) + in update_desc_tail_ptr()
1339 sys_write32(reg_val, reg_addr); in update_desc_tail_ptr()
1520 mem_addr_t reg_addr; in get_free_mac_addr_indx() local
1524 reg_addr = ioaddr + XGMAC_CORE_ADDRx_HIGH(idx); in get_free_mac_addr_indx()
1525 reg_val = sys_read32(reg_addr); in get_free_mac_addr_indx()
1537 mem_addr_t reg_addr; in disable_filter_for_mac_addr() local
1540 reg_addr = ioaddr + XGMAC_CORE_ADDRx_HIGH(idx) + 2u; in disable_filter_for_mac_addr()
1541 if (!(memcmp((uint8_t *)reg_addr, addr, 6u))) { in disable_filter_for_mac_addr()