153 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_dma_init()  local
155 		(mem_addr_t)(ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_SYSBUS_MODE_OFST);  in dwxgmac_dma_init()
177 	reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_TX_EDMA_CONTROL_OFST;  in dwxgmac_dma_init()
184 	reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_RX_EDMA_CONTROL_OFST;  in dwxgmac_dma_init()
203 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_dma_chnl_init()  local
214 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
225 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
236 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
244 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
251 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
257 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
263 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
269 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
275 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
281 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
287 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in dwxgmac_dma_chnl_init()
341 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_dma_mtl_init()  local
345 		(mem_addr_t)(ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_OPERATION_MODE_OFST);  in dwxgmac_dma_mtl_init()
352 		reg_addr = (ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_TC_PRTY_MAP0_OFST +  in dwxgmac_dma_mtl_init()
370 		reg_addr = (ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_RXQ_DMA_MAP0_OFST +  in dwxgmac_dma_mtl_init()
380 		reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) +  in dwxgmac_dma_mtl_init()
391 		reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) +  in dwxgmac_dma_mtl_init()
396 		reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) +  in dwxgmac_dma_mtl_init()
417 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_set_mac_addr_by_idx()  local
431 		    ioaddr + XGMAC_CORE_ADDRx_HIGH(idx));  in dwxgmac_set_mac_addr_by_idx()
436 	sys_write32(reg_val, ioaddr + XGMAC_CORE_ADDRx_LOW(idx));  in dwxgmac_set_mac_addr_by_idx()
445 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_update_link_speed()  local
448 	reg_val = sys_read32(ioaddr + CORE_MAC_TX_CONFIGURATION_OFST);  in eth_dwc_xgmac_update_link_speed()
468 	sys_write32(reg_val, ioaddr + CORE_MAC_TX_CONFIGURATION_OFST);  in eth_dwc_xgmac_update_link_speed()
476 	uint32_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_mac_init()  local
491 	sys_write32(reg_val, ioaddr + CORE_MAC_PACKET_FILTER_OFST);  in dwxgmac_mac_init()
498 	sys_write32(reg_val, ioaddr + CORE_MAC_RXQ_CTRL0_OFST);  in dwxgmac_mac_init()
502 	sys_write32(reg_val, ioaddr + CORE_MAC_TX_CONFIGURATION_OFST);  in dwxgmac_mac_init()
518 	sys_write32(reg_val, ioaddr + CORE_MAC_RX_CONFIGURATION_OFST);  in dwxgmac_mac_init()
529 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in dwxgmac_irq_init()  local
531 	reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_MODE_OFST;  in dwxgmac_irq_init()
879 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_isr()  local
886 			sys_read32(ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_INTERRUPT_STATUS_OFST);  in eth_dwc_xgmac_isr()
890 					sys_read32(ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) +  in eth_dwc_xgmac_isr()
898 				sys_write32(reg_val, (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) +  in eth_dwc_xgmac_isr()
912 	reg_addr = ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_INTERRUPT_STATUS_OFST;  in eth_dwc_xgmac_isr()
920 			reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) +  in eth_dwc_xgmac_isr()
938 	reg_addr = ioaddr + XGMAC_MTL_BASE_ADDR_OFFSET + MTL_INTERRUPT_STATUS_OFST;  in eth_dwc_xgmac_isr()
946 	reg_addr = ioaddr + XGMAC_CORE_BASE_ADDR_OFFSET + CORE_MAC_INTERRUPT_STATUS_OFST;  in eth_dwc_xgmac_isr()
988 	mem_addr_t ioaddr;  in eth_dwc_xgmac_dev_init()  local
991 	ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_dev_init()
1079 	mem_addr_t ioaddr;  in eth_dwc_xgmac_prefill_rx_desc()  local
1083 	ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_prefill_rx_desc()
1133 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_prefill_rx_desc()
1198 	mem_addr_t ioaddr;  in eth_dwc_xgmac_start_device()  local
1207 	ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_start_device()
1211 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_start_device()
1216 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_start_device()
1221 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_start_device()
1238 	reg_val = sys_read32(ioaddr + CORE_MAC_TX_CONFIGURATION_OFST);  in eth_dwc_xgmac_start_device()
1240 	sys_write32(reg_val, (ioaddr + CORE_MAC_TX_CONFIGURATION_OFST));  in eth_dwc_xgmac_start_device()
1242 	reg_val = sys_read32(ioaddr + CORE_MAC_RX_CONFIGURATION_OFST);  in eth_dwc_xgmac_start_device()
1244 	sys_write32(reg_val, (ioaddr + CORE_MAC_RX_CONFIGURATION_OFST));  in eth_dwc_xgmac_start_device()
1246 	reg_val = sys_read32(ioaddr + CORE_MAC_INTERRUPT_ENABLE_OFST);  in eth_dwc_xgmac_start_device()
1248 	sys_write32(reg_val, (ioaddr + CORE_MAC_INTERRUPT_ENABLE_OFST));  in eth_dwc_xgmac_start_device()
1276 	mem_addr_t ioaddr;  in eth_dwc_xgmac_stop_device()  local
1286 	ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_stop_device()
1290 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_stop_device()
1295 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_stop_device()
1300 		reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in eth_dwc_xgmac_stop_device()
1307 	reg_val = sys_read32(ioaddr + CORE_MAC_TX_CONFIGURATION_OFST);  in eth_dwc_xgmac_stop_device()
1309 	sys_write32(reg_val, (ioaddr + CORE_MAC_TX_CONFIGURATION_OFST));  in eth_dwc_xgmac_stop_device()
1311 	reg_val = sys_read32(ioaddr + CORE_MAC_RX_CONFIGURATION_OFST);  in eth_dwc_xgmac_stop_device()
1313 	sys_write32(reg_val, (ioaddr + CORE_MAC_RX_CONFIGURATION_OFST));  in eth_dwc_xgmac_stop_device()
1315 	reg_addr = ioaddr + CORE_MAC_INTERRUPT_ENABLE_OFST;  in eth_dwc_xgmac_stop_device()
1333 	mem_addr_t reg_addr, ioaddr = get_reg_base_addr(dev);  in update_desc_tail_ptr()  local
1336 	reg_addr = (ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(dma_chnl) +  in update_desc_tail_ptr()
1519 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in get_free_mac_addr_indx()  local
1524 		reg_addr = ioaddr + XGMAC_CORE_ADDRx_HIGH(idx);  in get_free_mac_addr_indx()
1536 	mem_addr_t ioaddr = get_reg_base_addr(dev);  in disable_filter_for_mac_addr()  local
1540 		reg_addr = ioaddr + XGMAC_CORE_ADDRx_HIGH(idx) + 2u;  in disable_filter_for_mac_addr()
1626 		mem_addr_t ioaddr = get_reg_base_addr(dev);  in eth_dwc_xgmac_set_config()  local
1629 			uint32_t reg_val = sys_read32(ioaddr + CORE_MAC_PACKET_FILTER_OFST);  in eth_dwc_xgmac_set_config()
1634 			sys_write32(reg_val, ioaddr + CORE_MAC_PACKET_FILTER_OFST);  in eth_dwc_xgmac_set_config()
1653 					ioaddr, (uint8_t *)config->filter.mac_address.addr, mac_idx,  in eth_dwc_xgmac_set_config()