Lines Matching +full:de +full:- +full:assert +full:- +full:time
5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
40 * length specified is non-zero.
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
77 * ------------------------------------------------------------------------|
79 * ------------------------------------------------------------------------|
81 * ------------------------------------------------------------------------|
88 * ------------------------------------------------------------------------|
90 * ------------------------------------------------------------------------|
161 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr; in xec_msvw_addr()
169 uintptr_t vwbase = ESPI_XEC_CONFIG(dev)->vw_base_addr; in xec_smvw_addr()
179 uint8_t cap0 = iom_regs->CAP0; in espi_xec_configure()
180 uint8_t cap1 = iom_regs->CAP1; in espi_xec_configure()
187 switch (cfg->max_freq) { in espi_xec_configure()
204 return -EINVAL; in espi_xec_configure()
208 iomode = (cfg->io_caps >> 1); in espi_xec_configure()
210 return -EINVAL; in espi_xec_configure()
221 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) { in espi_xec_configure()
225 return -EINVAL; in espi_xec_configure()
229 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) { in espi_xec_configure()
233 return -EINVAL; in espi_xec_configure()
237 if (cfg->channel_caps & ESPI_CHANNEL_OOB) { in espi_xec_configure()
241 return -EINVAL; in espi_xec_configure()
245 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) { in espi_xec_configure()
250 return -EINVAL; in espi_xec_configure()
254 iom_regs->CAP0 = cap0; in espi_xec_configure()
255 iom_regs->CAP1 = cap1; in espi_xec_configure()
259 * de-assertion and after pinmux in espi_xec_configure()
261 iom_regs->ACTV = 1; in espi_xec_configure()
275 sts = iom_regs->PCRDY & MCHP_ESPI_PC_READY; in espi_xec_channel_ready()
278 sts = iom_regs->VWRDY & MCHP_ESPI_VW_READY; in espi_xec_channel_ready()
281 sts = iom_regs->OOBRDY & MCHP_ESPI_OOB_READY; in espi_xec_channel_ready()
284 sts = iom_regs->FCRDY & MCHP_ESPI_FC_READY; in espi_xec_channel_ready()
305 return -EINVAL; in espi_xec_send_vwire()
309 return -EIO; /* VW not enabled */ in espi_xec_send_vwire()
330 while (sys_read8(regaddr + SMVW_BI_SRC_CHG) && rd_cnt--) { in espi_xec_send_vwire()
350 return -EINVAL; in espi_xec_receive_vwire()
354 return -EIO; /* VW not enabled */ in espi_xec_receive_vwire()
385 if (!(regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_CHEN)) { in espi_xec_send_oob()
387 return -EIO; in espi_xec_send_oob()
390 if (regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_BUSY) { in espi_xec_send_oob()
392 return -EBUSY; in espi_xec_send_oob()
395 if (pckt->len > CONFIG_ESPI_OOB_BUFFER_SIZE) { in espi_xec_send_oob()
397 return -EINVAL; in espi_xec_send_oob()
400 memcpy(target_tx_mem, pckt->buf, pckt->len); in espi_xec_send_oob()
402 regs->OOBTXL = pckt->len; in espi_xec_send_oob()
403 regs->OOBTXC = MCHP_ESPI_OOB_TX_CTRL_START; in espi_xec_send_oob()
404 LOG_DBG("%s %d", __func__, regs->OOBTXL); in espi_xec_send_oob()
407 ret = k_sem_take(&data->tx_lock, K_MSEC(MAX_OOB_TIMEOUT)); in espi_xec_send_oob()
408 if (ret == -EAGAIN) { in espi_xec_send_oob()
409 return -ETIMEDOUT; in espi_xec_send_oob()
412 if (regs->OOBTXSTS & err_mask) { in espi_xec_send_oob()
413 LOG_ERR("Tx failed %x", regs->OOBTXSTS); in espi_xec_send_oob()
414 regs->OOBTXSTS = err_mask; in espi_xec_send_oob()
415 return -EIO; in espi_xec_send_oob()
428 if (regs->OOBRXSTS & err_mask) { in espi_xec_receive_oob()
429 return -EIO; in espi_xec_receive_oob()
434 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data); in espi_xec_receive_oob()
437 ret = k_sem_take(&data->rx_lock, K_MSEC(MAX_OOB_TIMEOUT)); in espi_xec_receive_oob()
438 if (ret == -EAGAIN) { in espi_xec_receive_oob()
439 return -ETIMEDOUT; in espi_xec_receive_oob()
443 uint32_t rcvd_len = regs->OOBRXL & MCHP_ESPI_OOB_RX_LEN_MASK; in espi_xec_receive_oob()
445 if (rcvd_len > pckt->len) { in espi_xec_receive_oob()
446 LOG_ERR("space rcvd %d vs %d", rcvd_len, pckt->len); in espi_xec_receive_oob()
447 return -EIO; in espi_xec_receive_oob()
450 pckt->len = rcvd_len; in espi_xec_receive_oob()
451 memcpy(pckt->buf, target_rx_mem, pckt->len); in espi_xec_receive_oob()
452 memset(target_rx_mem, 0, pckt->len); in espi_xec_receive_oob()
457 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL; in espi_xec_receive_oob()
469 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data); in espi_xec_flash_read()
477 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_read()
479 return -EIO; in espi_xec_flash_read()
482 if (pckt->len > CONFIG_ESPI_FLASH_BUFFER_SIZE) { in espi_xec_flash_read()
484 return -EINVAL; in espi_xec_flash_read()
487 regs->FCFA[1] = 0; in espi_xec_flash_read()
488 regs->FCFA[0] = pckt->flash_addr; in espi_xec_flash_read()
489 regs->FCBA[1] = 0; in espi_xec_flash_read()
490 regs->FCBA[0] = (uint32_t)&target_mem[0]; in espi_xec_flash_read()
491 regs->FCLEN = pckt->len; in espi_xec_flash_read()
492 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_RD0); in espi_xec_flash_read()
493 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START; in espi_xec_flash_read()
496 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT)); in espi_xec_flash_read()
497 if (ret == -EAGAIN) { in espi_xec_flash_read()
499 return -ETIMEDOUT; in espi_xec_flash_read()
502 if (regs->FCSTS & err_mask) { in espi_xec_flash_read()
504 regs->FCSTS = err_mask; in espi_xec_flash_read()
505 return -EIO; in espi_xec_flash_read()
508 memcpy(pckt->buf, target_mem, pckt->len); in espi_xec_flash_read()
523 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data); in espi_xec_flash_write()
527 if (sizeof(target_mem) < pckt->len) { in espi_xec_flash_write()
529 return -ENOMEM; in espi_xec_flash_write()
532 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_write()
534 return -EIO; in espi_xec_flash_write()
537 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) { in espi_xec_flash_write()
539 return -EBUSY; in espi_xec_flash_write()
542 memcpy(target_mem, pckt->buf, pckt->len); in espi_xec_flash_write()
544 regs->FCFA[1] = 0; in espi_xec_flash_write()
545 regs->FCFA[0] = pckt->flash_addr; in espi_xec_flash_write()
546 regs->FCBA[1] = 0; in espi_xec_flash_write()
547 regs->FCBA[0] = (uint32_t)&target_mem[0]; in espi_xec_flash_write()
548 regs->FCLEN = pckt->len; in espi_xec_flash_write()
549 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_WR0); in espi_xec_flash_write()
550 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START; in espi_xec_flash_write()
553 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT)); in espi_xec_flash_write()
554 if (ret == -EAGAIN) { in espi_xec_flash_write()
556 return -ETIMEDOUT; in espi_xec_flash_write()
559 if (regs->FCSTS & err_mask) { in espi_xec_flash_write()
561 regs->FCSTS = err_mask; in espi_xec_flash_write()
562 return -EIO; in espi_xec_flash_write()
579 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data); in espi_xec_flash_erase()
583 if (!(regs->FCSTS & MCHP_ESPI_FC_STS_CHAN_EN)) { in espi_xec_flash_erase()
585 return -EIO; in espi_xec_flash_erase()
588 if ((regs->FCCFG & MCHP_ESPI_FC_CFG_BUSY)) { in espi_xec_flash_erase()
590 return -EBUSY; in espi_xec_flash_erase()
594 status = regs->FCSTS; in espi_xec_flash_erase()
595 regs->FCSTS = status; in espi_xec_flash_erase()
597 regs->FCFA[1] = 0; in espi_xec_flash_erase()
598 regs->FCFA[0] = pckt->flash_addr; in espi_xec_flash_erase()
599 regs->FCLEN = ESPI_FLASH_ERASE_DUMMY; in espi_xec_flash_erase()
600 regs->FCCTL = MCHP_ESPI_FC_CTRL_FUNC(MCHP_ESPI_FC_CTRL_ERS0); in espi_xec_flash_erase()
601 regs->FCCTL |= MCHP_ESPI_FC_CTRL_START; in espi_xec_flash_erase()
604 ret = k_sem_take(&data->flash_lock, K_MSEC(MAX_FLASH_TIMEOUT)); in espi_xec_flash_erase()
605 if (ret == -EAGAIN) { in espi_xec_flash_erase()
607 return -ETIMEDOUT; in espi_xec_flash_erase()
610 if (regs->FCSTS & err_mask) { in espi_xec_flash_erase()
612 regs->FCSTS = err_mask; in espi_xec_flash_erase()
613 return -EIO; in espi_xec_flash_erase()
625 return espi_manage_callback(&data->callbacks, callback, set); in espi_xec_manage_callback()
651 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_up_girq_idx].gid, in espi_init_oob()
652 cfg->irq_info_list[oob_up_girq_idx].gpos); in espi_init_oob()
653 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[oob_dn_girq_idx].gid, in espi_init_oob()
654 cfg->irq_info_list[oob_dn_girq_idx].gpos); in espi_init_oob()
656 regs->OOBTXA[1] = 0; in espi_init_oob()
657 regs->OOBRXA[1] = 0; in espi_init_oob()
658 regs->OOBTXA[0] = (uint32_t)&target_tx_mem[0]; in espi_init_oob()
659 regs->OOBRXA[0] = (uint32_t)&target_rx_mem[0]; in espi_init_oob()
660 regs->OOBRXL = 0x00FF0000; in espi_init_oob()
663 regs->OOBTXIEN |= MCHP_ESPI_OOB_TX_IEN_CHG_EN | in espi_init_oob()
666 /* Enable Rx channel to receive data any time in espi_init_oob()
669 regs->OOBRXIEN |= MCHP_ESPI_OOB_RX_IEN; in espi_init_oob()
670 regs->OOBRXC |= MCHP_ESPI_OOB_RX_CTRL_AVAIL; in espi_init_oob()
683 LOG_DBG("%s ESPI_FC_REGS->CFG %X", __func__, regs->FCCFG); in espi_init_flash()
684 regs->FCSTS = MCHP_ESPI_FC_STS_DONE; in espi_init_flash()
687 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[fc_girq_idx].gid, in espi_init_flash()
688 cfg->irq_info_list[fc_girq_idx].gpos); in espi_init_flash()
689 regs->FCIEN |= MCHP_ESPI_FC_IEN_CHG_EN; in espi_init_flash()
690 regs->FCIEN |= MCHP_ESPI_FC_IEN_DONE; in espi_init_flash()
699 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[pc_girq_idx].gid, in espi_bus_init()
700 cfg->irq_info_list[pc_girq_idx].gpos); in espi_bus_init()
701 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[rst_girq_idx].gid, in espi_bus_init()
702 cfg->irq_info_list[rst_girq_idx].gpos); in espi_bus_init()
703 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[vw_ch_en_girq_idx].gid, in espi_bus_init()
704 cfg->irq_info_list[vw_ch_en_girq_idx].gpos); in espi_bus_init()
714 return -EINVAL; in xec_espi_bus_intr_clr()
717 mchp_xec_ecia_girq_src_clr(cfg->irq_info_list[idx].gid, in xec_espi_bus_intr_clr()
718 cfg->irq_info_list[idx].gpos); in xec_espi_bus_intr_clr()
731 return -EINVAL; in xec_espi_bus_intr_ctl()
735 mchp_xec_ecia_girq_src_en(cfg->irq_info_list[idx].gid, in xec_espi_bus_intr_ctl()
736 cfg->irq_info_list[idx].gpos); in xec_espi_bus_intr_ctl()
738 mchp_xec_ecia_girq_src_dis(cfg->irq_info_list[idx].gid, in xec_espi_bus_intr_ctl()
739 cfg->irq_info_list[idx].gpos); in xec_espi_bus_intr_ctl()
753 data->espi_rst_count++; in espi_rst_isr()
756 rst_sts = regs->ERIS; in espi_rst_isr()
759 regs->ERIS = MCHP_ESPI_RST_ISTS; in espi_rst_isr()
770 espi_send_callbacks(&data->callbacks, dev, evt); in espi_rst_isr()
797 regs->SIRQ[SIRQ_UART0] = UART_DEFAULT_IRQ; in configure_sirq()
800 regs->SIRQ[SIRQ_UART1] = UART_DEFAULT_IRQ; in configure_sirq()
805 regs->SIRQ[SIRQ_KBC_KIRQ] = 1; in configure_sirq()
806 regs->SIRQ[SIRQ_KBC_MIRQ] = 12; in configure_sirq()
815 regs->IOHBAR[IOB_IOC] = (host_address << 16) | in setup_espi_io_config()
821 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG | in setup_espi_io_config()
823 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG; in setup_espi_io_config()
824 regs->PCRDY = 1; in setup_espi_io_config()
838 return -EINVAL; in xec_espi_vw_intr_ctrl()
841 uintptr_t msvw_addr = (uintptr_t)®s->MSVW[msvw_idx]; in xec_espi_vw_intr_ctrl()
851 uint32_t status = regs->PCSTS; in espi_pc_isr()
855 struct espi_xec_data *data = (struct espi_xec_data *)(dev->data); in espi_pc_isr()
860 regs->PCSTS = MCHP_ESPI_PC_STS_BUS_ERR; in espi_pc_isr()
868 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG; in espi_pc_isr()
875 espi_send_callbacks(&data->callbacks, dev, evt); in espi_pc_isr()
878 regs->PCSTS = MCHP_ESPI_PC_STS_BM_EN_CHG; in espi_pc_isr()
891 uint32_t status = regs->VWSTS; in espi_vw_chan_en_isr()
894 regs->VWRDY = 1; in espi_vw_chan_en_isr()
904 espi_send_callbacks(&data->callbacks, dev, evt); in espi_vw_chan_en_isr()
921 status = regs->OOBRXSTS; in espi_oob_down_isr()
925 /* Register is write-on-clear, ensure only 1 bit is affected */ in espi_oob_down_isr()
926 regs->OOBRXSTS = MCHP_ESPI_OOB_RX_STS_DONE; in espi_oob_down_isr()
929 k_sem_give(&data->rx_lock); in espi_oob_down_isr()
931 evt.evt_details = regs->OOBRXL & in espi_oob_down_isr()
933 espi_send_callbacks(&data->callbacks, dev, evt); in espi_oob_down_isr()
950 status = regs->OOBTXSTS; in espi_oob_up_isr()
954 /* Register is write-on-clear, ensure only 1 bit is affected */ in espi_oob_up_isr()
955 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_DONE; in espi_oob_up_isr()
956 k_sem_give(&data->tx_lock); in espi_oob_up_isr()
963 regs->OOBRDY = 1; in espi_oob_up_isr()
967 status = regs->OOBTXSTS = MCHP_ESPI_OOB_TX_STS_CHG_EN; in espi_oob_up_isr()
968 espi_send_callbacks(&data->callbacks, dev, evt); in espi_oob_up_isr()
986 status = regs->FCSTS; in espi_flash_isr()
991 regs->FCSTS = MCHP_ESPI_FC_STS_DONE; in espi_flash_isr()
993 k_sem_give(&data->flash_lock); in espi_flash_isr()
998 regs->FCSTS = MCHP_ESPI_FC_STS_CHAN_EN_CHG; in espi_flash_isr()
1003 regs->FCRDY = MCHP_ESPI_FC_READY; in espi_flash_isr()
1007 espi_send_callbacks(&data->callbacks, dev, evt); in espi_flash_isr()
1025 espi_send_callbacks(&data->callbacks, dev, evt); in notify_system_state()
1041 espi_send_callbacks(&data->callbacks, dev, evt); in notify_host_warning()
1082 espi_send_callbacks(&data->callbacks, dev, evt); in notify_vw_status()
1171 espi_send_callbacks(&data->callbacks, dev, evt); in vw_pltrst_handler()
1274 /* n = node-id, p = property, i = index */
1360 /* MSVW is a 96-bit register and SMVW is a 64-bit register.
1371 uint8_t src_pos = (8u * p->bit); in xec_vw_cfg_properties()
1372 uint8_t rst_state = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_STATE_POS) in xec_vw_cfg_properties()
1374 uint8_t rst_src = rst_src = (p->flags >> MCHP_DT_ESPI_VW_FLAG_RST_SRC_POS) in xec_vw_cfg_properties()
1387 rst_state--; in xec_vw_cfg_properties()
1389 temp |= BIT(p->bit + 4u); in xec_vw_cfg_properties()
1392 temp |= ~BIT(p->bit + 4u); in xec_vw_cfg_properties()
1398 rst_src--; in xec_vw_cfg_properties()
1405 if (sys_read8(regaddr) != p->host_idx) { in xec_vw_cfg_properties()
1406 sys_write8(p->host_idx, regaddr); in xec_vw_cfg_properties()
1419 uint32_t regaddr = xec_smvw_addr(dev, p->xec_reg_idx); in xec_vw_config()
1420 uint8_t dir = (p->flags >> MCHP_DT_ESPI_VW_FLAG_DIR_POS) & BIT(0); in xec_vw_config()
1421 uint8_t en = (p->flags & BIT(MCHP_DT_ESPI_VW_FLAG_STATUS_POS)); in xec_vw_config()
1424 regaddr = xec_msvw_addr(dev, p->xec_reg_idx); in xec_vw_config()
1437 struct xec_signal signal_info = vw_tbl[vwi->signal]; in xec_register_vw_handlers()
1442 LOG_INF("VW %d not enabled, skipping", vwi->signal); in xec_register_vw_handlers()
1451 int ret = mchp_xec_ecia_set_callback(vwi->girq_id, vwi->girq_pos, in xec_register_vw_handlers()
1452 vwi->the_isr, (void *)dev); in xec_register_vw_handlers()
1454 return -EIO; in xec_register_vw_handlers()
1457 mchp_xec_ecia_girq_src_en(vwi->girq_id, vwi->girq_pos); in xec_register_vw_handlers()
1469 * The VW count is a zero based 6-bit value: (0 - 63) specifying the number of
1486 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in espi_xec_init()
1493 data->espi_rst_count = 0; in espi_xec_init()
1496 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_bitpos, 0); in espi_xec_init()
1500 * RESET_VCC to de-assert. Host facing peripherals will no longer in espi_xec_init()
1503 pcr->PWR_RST_CTRL = MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST; in espi_xec_init()
1504 regs->PLTSRC = MCHP_ESPI_PLTRST_SRC_IS_VW; in espi_xec_init()
1507 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_VW_SUPP | MCHP_ESPI_GBL_CAP0_PC_SUPP; in espi_xec_init()
1509 regs->CAPVW = MAX(ESPI_NUM_MSVW, ESPI_NUM_SMVW); in espi_xec_init()
1510 regs->CAPPC |= MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64; in espi_xec_init()
1513 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_OOB_SUPP; in espi_xec_init()
1514 regs->CAPOOB |= MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73; in espi_xec_init()
1516 k_sem_init(&data->tx_lock, 0, 1); in espi_xec_init()
1518 k_sem_init(&data->rx_lock, 0, 1); in espi_xec_init()
1521 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_OOB_SUPP; in espi_xec_init()
1525 regs->CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP | in espi_xec_init()
1527 regs->CAPFC |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF | in espi_xec_init()
1530 k_sem_init(&data->flash_lock, 0, 1); in espi_xec_init()
1532 regs->CAP0 &= ~MCHP_ESPI_GBL_CAP0_FC_SUPP; in espi_xec_init()
1536 regs->ERIS = MCHP_ESPI_RST_ISTS; in espi_xec_init()
1537 regs->ERIE |= MCHP_ESPI_RST_IEN; in espi_xec_init()
1538 regs->PCSTS = MCHP_ESPI_PC_STS_EN_CHG; in espi_xec_init()
1539 regs->PCIEN |= MCHP_ESPI_PC_IEN_EN_CHG; in espi_xec_init()