Lines Matching full:dma
13 #include <zephyr/drivers/dma.h>
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
41 XMC_DMA_t *dma; member
53 uint32_t channels_event = get_channels_event(dma); \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
75 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_isr() local
79 /* There are two types of possible DMA error events: */ in dma_xmc4xxx_isr()
80 /* 1. Error response from AHB slave on the HRESP bus during DMA transfer. */ in dma_xmc4xxx_isr()
85 event = XMC_DMA_GetEventStatus(dma); in dma_xmc4xxx_isr()
128 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_config() local
159 if (dma != XMC_DMA0 || channel >= 2) { in dma_xmc4xxx_config()
194 if (XMC_DMA_CH_IsEnabled(dma, channel)) { in dma_xmc4xxx_config()
199 XMC_DMA_CH_ClearEventStatus(dma, channel, ALL_EVENTS); in dma_xmc4xxx_config()
201 /* check dma slot number */ in dma_xmc4xxx_config()
202 dma->CH[channel].SAR = block->source_address; in dma_xmc4xxx_config()
203 dma->CH[channel].DAR = block->dest_address; in dma_xmc4xxx_config()
204 dma->CH[channel].LLP = 0; in dma_xmc4xxx_config()
207 dma->CH[channel].CTLH = block->block_size / config->source_data_size; in dma_xmc4xxx_config()
210 dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) | in dma_xmc4xxx_config()
213 dma->CH[channel].CTLL = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos | in dma_xmc4xxx_config()
227 if (dma == XMC_DMA0 && dlr_line > 7) { in dma_xmc4xxx_config()
233 if (dma == XMC_DMA1 && (dlr_line < 8 || dlr_line > 11)) { in dma_xmc4xxx_config()
241 /* enable the dma line */ in dma_xmc4xxx_config()
245 /* connect DMA Line to SR */ in dma_xmc4xxx_config()
246 if (dma == XMC_DMA0) { in dma_xmc4xxx_config()
251 if (dma == XMC_DMA1) { in dma_xmc4xxx_config()
257 /* connect DMA channel to DMA line */ in dma_xmc4xxx_config()
259 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4; in dma_xmc4xxx_config()
260 dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_DST_Pos); in dma_xmc4xxx_config()
261 dma->CH[channel].CTLL |= 1 << GPDMA0_CH_CTLL_TT_FC_Pos; in dma_xmc4xxx_config()
265 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_SRC_PER_Pos) | 4; in dma_xmc4xxx_config()
266 dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_SRC_Pos); in dma_xmc4xxx_config()
267 dma->CH[channel].CTLL |= 2 << GPDMA0_CH_CTLL_TT_FC_Pos; in dma_xmc4xxx_config()
272 dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos); in dma_xmc4xxx_config()
274 dma->CH[channel].SGR = (block->source_gather_interval & GPDMA0_CH_SGR_SGI_Msk) | in dma_xmc4xxx_config()
279 dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos); in dma_xmc4xxx_config()
281 dma->CH[channel].DSR = (block->dest_scatter_interval & GPDMA0_CH_DSR_DSI_Msk) | in dma_xmc4xxx_config()
291 XMC_DMA_CH_DisableEvent(dma, channel, ALL_EVENTS); in dma_xmc4xxx_config()
292 XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE); in dma_xmc4xxx_config()
296 XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); in dma_xmc4xxx_config()
300 XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_ERROR); in dma_xmc4xxx_config()
314 XMC_DMA_CH_Enable(dev_cfg->dma, channel); in dma_xmc4xxx_start()
323 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_stop() local
326 XMC_DMA_CH_Suspend(dma, channel); in dma_xmc4xxx_stop()
329 while (XMC_DMA_CH_IsEnabled(dma, channel) && in dma_xmc4xxx_stop()
330 (dma->CH[channel].CFGL & GPDMA0_CH_CFGL_FIFO_EMPTY_Msk) == 0) { in dma_xmc4xxx_stop()
341 XMC_DMA_CH_Disable(dma, channel); in dma_xmc4xxx_stop()
351 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_reload() local
359 if (XMC_DMA_CH_IsEnabled(dma, channel)) { in dma_xmc4xxx_reload()
373 dma->CH[channel].SAR = src; in dma_xmc4xxx_reload()
374 dma->CH[channel].DAR = dst; in dma_xmc4xxx_reload()
375 dma->CH[channel].CTLH = block_ts; in dma_xmc4xxx_reload()
385 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_get_status() local
394 stat->busy = XMC_DMA_CH_IsEnabled(dma, channel); in dma_xmc4xxx_get_status()
396 stat->pending_length = dma_channel->block_ts - XMC_DMA_CH_GetTransferredData(dma, channel); in dma_xmc4xxx_get_status()
425 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_suspend() local
432 XMC_DMA_CH_Suspend(dma, channel); in dma_xmc4xxx_suspend()
440 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_resume() local
447 XMC_DMA_CH_Resume(dma, channel); in dma_xmc4xxx_resume()
455 XMC_DMA_Enable(dev_cfg->dma); in dma_xmc4xxx_init()
460 static DEVICE_API(dma, dma_xmc4xxx_driver_api) = {
481 .dma = (XMC_DMA_t *)DT_INST_REG_ADDR(inst), \