Lines Matching full:ch
202 dma->CH[channel].SAR = block->source_address; in dma_xmc4xxx_config()
203 dma->CH[channel].DAR = block->dest_address; in dma_xmc4xxx_config()
204 dma->CH[channel].LLP = 0; in dma_xmc4xxx_config()
207 dma->CH[channel].CTLH = block->block_size / config->source_data_size; in dma_xmc4xxx_config()
210 dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) | in dma_xmc4xxx_config()
213 dma->CH[channel].CTLL = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos | in dma_xmc4xxx_config()
259 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4; in dma_xmc4xxx_config()
260 dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_DST_Pos); in dma_xmc4xxx_config()
261 dma->CH[channel].CTLL |= 1 << GPDMA0_CH_CTLL_TT_FC_Pos; in dma_xmc4xxx_config()
265 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_SRC_PER_Pos) | 4; in dma_xmc4xxx_config()
266 dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_SRC_Pos); in dma_xmc4xxx_config()
267 dma->CH[channel].CTLL |= 2 << GPDMA0_CH_CTLL_TT_FC_Pos; in dma_xmc4xxx_config()
272 dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos); in dma_xmc4xxx_config()
274 dma->CH[channel].SGR = (block->source_gather_interval & GPDMA0_CH_SGR_SGI_Msk) | in dma_xmc4xxx_config()
279 dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos); in dma_xmc4xxx_config()
281 dma->CH[channel].DSR = (block->dest_scatter_interval & GPDMA0_CH_DSR_DSI_Msk) | in dma_xmc4xxx_config()
330 (dma->CH[channel].CFGL & GPDMA0_CH_CFGL_FIFO_EMPTY_Msk) == 0) { in dma_xmc4xxx_stop()
373 dma->CH[channel].SAR = src; in dma_xmc4xxx_reload()
374 dma->CH[channel].DAR = dst; in dma_xmc4xxx_reload()
375 dma->CH[channel].CTLH = block_ts; in dma_xmc4xxx_reload()