186 	uint32_t dmasr;  member
385 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
388 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
392 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
395 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
399 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
402 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
406 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
409 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
413 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
416 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
420 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
423 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
529 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmasr, 0xffffffff);  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
620 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_start()
748 	stat->busy = !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()
750 		     !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()