247 	volatile struct dma_xilinx_axi_dma_mm2s_s2mm_registers *channel_regs;  member
370 	uint32_t dmacr = dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmacr);  in dma_xilinx_axi_dma_acknowledge_interrupt()
372 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, dmacr);  in dma_xilinx_axi_dma_acknowledge_interrupt()
385 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
388 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
392 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
395 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
399 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
402 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
406 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
409 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
413 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
416 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
420 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
423 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
529 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmasr, 0xffffffff);  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
620 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_start()
629 			&channel_data->channel_regs->curdesc,  in dma_xilinx_axi_dma_start()
632 			&channel_data->channel_regs->curdesc_msb,  in dma_xilinx_axi_dma_start()
635 		dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->curdesc,  in dma_xilinx_axi_dma_start()
674 		dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);  in dma_xilinx_axi_dma_start()
680 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc,  in dma_xilinx_axi_dma_start()
682 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc_msb,  in dma_xilinx_axi_dma_start()
685 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc,  in dma_xilinx_axi_dma_start()
716 	new_control = channel_data->channel_regs->dmacr;  in dma_xilinx_axi_dma_stop()
722 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);  in dma_xilinx_axi_dma_stop()
748 	stat->busy = !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()
750 		     !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()
935 		data->channels[channel].channel_regs = &regs->mm2s_registers;  in dma_xilinx_axi_dma_configure()
940 		data->channels[channel].channel_regs = &regs->s2mm_registers;  in dma_xilinx_axi_dma_configure()
952 		dma_xilinx_axi_dma_write_reg(&data->channels[channel].channel_regs->dmacr,  in dma_xilinx_axi_dma_configure()