365 dma_xilinx_axi_dma_acknowledge_interrupt(struct dma_xilinx_axi_dma_channel *channel_data)  in dma_xilinx_axi_dma_acknowledge_interrupt()  argument
370 	uint32_t dmacr = dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmacr);  in dma_xilinx_axi_dma_acknowledge_interrupt()
372 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, dmacr);  in dma_xilinx_axi_dma_acknowledge_interrupt()
379 	const struct dma_xilinx_axi_dma_channel *channel_data,  in dma_xilinx_axi_dma_channel_has_error()  argument
385 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
388 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
392 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
395 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
399 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
402 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
406 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
409 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
413 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
416 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
420 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_channel_has_error()
423 			dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr));  in dma_xilinx_axi_dma_channel_has_error()
448 					   struct dma_xilinx_axi_dma_channel *channel_data,  in dma_xilinx_axi_dma_clean_up_sg_descriptors()  argument
452 		&channel_data->descriptors[channel_data->current_transfer_end_index];  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
461 		channel_data->last_rx_size = current_descriptor->status &  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
464 		if (dma_xilinx_axi_dma_channel_has_error(channel_data, current_descriptor)) {  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
469 		if (channel_data->check_csum_in_isr) {  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
508 		channel_data->current_transfer_end_index++;  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
509 		if (channel_data->current_transfer_end_index >= channel_data->num_descriptors) {  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
510 			channel_data->current_transfer_end_index = 0;  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
513 		if (channel_data->completion_callback) {  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
514 			LOG_DBG("Received packet with %u bytes!", channel_data->last_rx_size);  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
515 			channel_data->completion_callback(  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
516 				dev, channel_data->completion_callback_user_data,  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
521 			&channel_data->descriptors[channel_data->current_transfer_end_index];  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
529 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmasr, 0xffffffff);  in dma_xilinx_axi_dma_clean_up_sg_descriptors()
541 	struct dma_xilinx_axi_dma_channel *channel_data =  in dma_xilinx_axi_dma_tx_isr()  local
547 	processed_packets = dma_xilinx_axi_dma_clean_up_sg_descriptors(dev, channel_data, "TX");  in dma_xilinx_axi_dma_tx_isr()
553 	dma_xilinx_axi_dma_acknowledge_interrupt(channel_data);  in dma_xilinx_axi_dma_tx_isr()
559 	struct dma_xilinx_axi_dma_channel *channel_data =  in dma_xilinx_axi_dma_rx_isr()  local
565 	processed_packets = dma_xilinx_axi_dma_clean_up_sg_descriptors(dev, channel_data, "RX");  in dma_xilinx_axi_dma_rx_isr()
571 	dma_xilinx_axi_dma_acknowledge_interrupt(channel_data);  in dma_xilinx_axi_dma_rx_isr()
584 	struct dma_xilinx_axi_dma_channel *channel_data = &data->channels[channel];  in dma_xilinx_axi_dma_start()  local
601 	tail_descriptor = channel_data->current_transfer_start_index++;  in dma_xilinx_axi_dma_start()
603 	if (channel_data->current_transfer_start_index >= channel_data->num_descriptors) {  in dma_xilinx_axi_dma_start()
606 		channel_data->current_transfer_start_index = 0;  in dma_xilinx_axi_dma_start()
610 	current_descriptor = &channel_data->descriptors[tail_descriptor];  in dma_xilinx_axi_dma_start()
612 		&channel_data->descriptors[channel_data->current_transfer_end_index];  in dma_xilinx_axi_dma_start()
616 		channel_data->current_transfer_end_index);  in dma_xilinx_axi_dma_start()
620 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_start()
629 			&channel_data->channel_regs->curdesc,  in dma_xilinx_axi_dma_start()
632 			&channel_data->channel_regs->curdesc_msb,  in dma_xilinx_axi_dma_start()
635 		dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->curdesc,  in dma_xilinx_axi_dma_start()
674 		dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);  in dma_xilinx_axi_dma_start()
680 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc,  in dma_xilinx_axi_dma_start()
682 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc_msb,  in dma_xilinx_axi_dma_start()
685 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc,  in dma_xilinx_axi_dma_start()
704 	struct dma_xilinx_axi_dma_channel *channel_data = &data->channels[channel];  in dma_xilinx_axi_dma_stop()  local
714 	k_timer_stop(&channel_data->polling_timer);  in dma_xilinx_axi_dma_stop()
716 	new_control = channel_data->channel_regs->dmacr;  in dma_xilinx_axi_dma_stop()
722 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);  in dma_xilinx_axi_dma_stop()
736 	struct dma_xilinx_axi_dma_channel *channel_data = &data->channels[channel];  in dma_xilinx_axi_dma_get_status()  local
748 	stat->busy = !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()
750 		     !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &  in dma_xilinx_axi_dma_get_status()
753 	stat->dir = channel_data->last_transfer_direction;  in dma_xilinx_axi_dma_get_status()
766 						    struct dma_xilinx_axi_dma_channel *channel_data,  in dma_xilinx_axi_dma_transfer_block()  argument
775 	current_descriptor = &channel_data->descriptors[channel_data->current_transfer_start_index];  in dma_xilinx_axi_dma_transfer_block()
785 	current_descriptor->app0 = channel_data->sg_desc_app0;  in dma_xilinx_axi_dma_transfer_block()
827 	struct dma_xilinx_axi_dma_channel *channel_data = &data->channels[channel];  in dma_xilinx_axi_dma_config_reload()  local
836 		cfg, channel, channel_data, channel == XILINX_AXI_DMA_TX_CHANNEL_NUM ? src : dst,  in dma_xilinx_axi_dma_config_reload()