Lines Matching refs:cfgr
100 uint32_t cfgr = 0; in dma_wch_config() local
126 cfgr |= DMA_CFGR1_MEM2MEM; in dma_wch_config()
137 cfgr |= DMA_CFGR1_DIR; in dma_wch_config()
146 cfgr |= dma_cfg->channel_priority * DMA_CFGR1_PL_0; in dma_wch_config()
149 cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) * in dma_wch_config()
151 cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) * in dma_wch_config()
154 cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT) in dma_wch_config()
157 cfgr |= (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT) in dma_wch_config()
161 cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) * in dma_wch_config()
163 cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) * in dma_wch_config()
166 cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT) in dma_wch_config()
169 cfgr |= (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT) in dma_wch_config()
175 cfgr |= DMA_CFGR1_CIRC; in dma_wch_config()
180 cfgr |= DMA_CFGR1_TEIE; in dma_wch_config()
184 cfgr |= DMA_CFGR1_HTIE; in dma_wch_config()
187 cfgr |= DMA_CFGR1_TCIE; in dma_wch_config()
211 regs->channels[ch].CFGR = cfgr; in dma_wch_config()
344 uint32_t cfgr; in dma_wch_get_status() local
352 cfgr = regs->channels[ch].CFGR; in dma_wch_get_status()
355 if (cfgr & DMA_CFGR1_MEM2MEM) { in dma_wch_get_status()
357 } else if (cfgr & DMA_CFGR1_DIR) { in dma_wch_get_status()
364 if (cfgr & DMA_CFGR1_DIR) { in dma_wch_get_status()