Lines Matching +full:periph +full:- +full:clock +full:- +full:config
5 * SPDX-License-Identifier: Apache-2.0
72 const struct dma_stm32_config *config = dev->config; in dma_stm32_dump_stream_irq() local
73 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq()
80 const struct dma_stm32_config *config = dev->config; in dma_stm32_clear_stream_irq() local
81 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq()
90 const struct dma_stm32_config *config = dev->config; in dma_stm32_irq_handler() local
91 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_irq_handler()
95 __ASSERT_NO_MSG(id < config->max_streams); in dma_stm32_irq_handler()
97 stream = &config->streams[id]; in dma_stm32_irq_handler()
100 if ((stream->hal_override != true) && (stream->busy == false)) { in dma_stm32_irq_handler()
109 callback_arg = stream->mux_channel; in dma_stm32_irq_handler()
114 /* The dma stream id is in range from STM32_DMA_STREAM_OFFSET..<dma-requests> */ in dma_stm32_irq_handler()
117 if (!stream->hal_override) { in dma_stm32_irq_handler()
120 stream->dma_callback(dev, stream->user_data, callback_arg, DMA_STATUS_BLOCK); in dma_stm32_irq_handler()
123 if (!stream->cyclic) { in dma_stm32_irq_handler()
124 stream->busy = false; in dma_stm32_irq_handler()
127 if (!stream->hal_override) { in dma_stm32_irq_handler()
130 stream->dma_callback(dev, stream->user_data, callback_arg, DMA_STATUS_COMPLETE); in dma_stm32_irq_handler()
133 stream->dma_callback(dev, stream->user_data, in dma_stm32_irq_handler()
134 callback_arg, -EIO); in dma_stm32_irq_handler()
137 stream->busy = false; in dma_stm32_irq_handler()
140 stream->dma_callback(dev, stream->user_data, in dma_stm32_irq_handler()
141 callback_arg, -EIO); in dma_stm32_irq_handler()
150 const struct dma_stm32_config *cfg_##index = dev_##index->config; \
151 DMA_TypeDef *dma_##index = (DMA_TypeDef *)(cfg_##index->base); \
153 for (id = 0; id < cfg_##index->max_streams; ++id) { \
186 return -EINVAL; in dma_stm32_get_priority()
207 return -EINVAL; in dma_stm32_get_direction()
224 return -ENOTSUP; in dma_stm32_get_memory_increment()
227 return -EINVAL; in dma_stm32_get_memory_increment()
244 return -ENOTSUP; in dma_stm32_get_periph_increment()
246 LOG_ERR("Periph increment error. %d", increment); in dma_stm32_get_periph_increment()
247 return -EINVAL; in dma_stm32_get_periph_increment()
263 return -EBUSY; in dma_stm32_disable_stream()
273 struct dma_config *config) in dma_stm32_configure() argument
275 const struct dma_stm32_config *dev_config = dev->config; in dma_stm32_configure()
277 &dev_config->streams[id - STM32_DMA_STREAM_OFFSET]; in dma_stm32_configure()
278 DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base; in dma_stm32_configure()
285 id = id - STM32_DMA_STREAM_OFFSET; in dma_stm32_configure()
287 if (id >= dev_config->max_streams) { in dma_stm32_configure()
289 return -EINVAL; in dma_stm32_configure()
292 if (stream->busy) { in dma_stm32_configure()
294 return -EBUSY; in dma_stm32_configure()
299 return -EBUSY; in dma_stm32_configure()
305 if (config->linked_channel == STM32_DMA_HAL_OVERRIDE) { in dma_stm32_configure()
310 stream->busy = true; in dma_stm32_configure()
311 stream->hal_override = true; in dma_stm32_configure()
312 stream->dma_callback = config->dma_callback; in dma_stm32_configure()
313 stream->user_data = config->user_data; in dma_stm32_configure()
314 stream->cyclic = false; in dma_stm32_configure()
318 if (config->head_block->block_size > DMA_STM32_MAX_DATA_ITEMS) { in dma_stm32_configure()
320 config->head_block->block_size); in dma_stm32_configure()
321 return -EINVAL; in dma_stm32_configure()
325 if ((config->channel_direction == MEMORY_TO_MEMORY) && in dma_stm32_configure()
326 (!dev_config->support_m2m)) { in dma_stm32_configure()
328 dev->name); in dma_stm32_configure()
329 return -ENOTSUP; in dma_stm32_configure()
334 if ((config->dest_data_size != config->source_data_size)) { in dma_stm32_configure()
336 return -EINVAL; in dma_stm32_configure()
339 if (config->source_data_size != 4U && in dma_stm32_configure()
340 config->source_data_size != 2U && in dma_stm32_configure()
341 config->source_data_size != 1U) { in dma_stm32_configure()
343 config->source_data_size); in dma_stm32_configure()
344 return -EINVAL; in dma_stm32_configure()
351 if (config->head_block->source_reload_en != in dma_stm32_configure()
352 config->head_block->dest_reload_en) { in dma_stm32_configure()
355 return -EINVAL; in dma_stm32_configure()
358 stream->busy = true; in dma_stm32_configure()
359 stream->dma_callback = config->dma_callback; in dma_stm32_configure()
360 stream->direction = config->channel_direction; in dma_stm32_configure()
361 stream->user_data = config->user_data; in dma_stm32_configure()
362 stream->src_size = config->source_data_size; in dma_stm32_configure()
363 stream->dst_size = config->dest_data_size; in dma_stm32_configure()
364 stream->cyclic = config->head_block->source_reload_en; in dma_stm32_configure()
367 if (config->head_block->source_address == 0) { in dma_stm32_configure()
371 if (config->head_block->dest_address == 0) { in dma_stm32_configure()
375 if (stream->direction == MEMORY_TO_PERIPHERAL) { in dma_stm32_configure()
377 config->head_block->source_address; in dma_stm32_configure()
379 config->head_block->dest_address; in dma_stm32_configure()
382 config->head_block->source_address; in dma_stm32_configure()
384 config->head_block->dest_address; in dma_stm32_configure()
389 ret = dma_stm32_get_priority(config->channel_priority, in dma_stm32_configure()
395 ret = dma_stm32_get_direction(config->channel_direction, in dma_stm32_configure()
401 switch (config->channel_direction) { in dma_stm32_configure()
404 memory_addr_adj = config->head_block->dest_addr_adj; in dma_stm32_configure()
405 periph_addr_adj = config->head_block->source_addr_adj; in dma_stm32_configure()
408 memory_addr_adj = config->head_block->source_addr_adj; in dma_stm32_configure()
409 periph_addr_adj = config->head_block->dest_addr_adj; in dma_stm32_configure()
414 config->channel_direction); in dma_stm32_configure()
415 return -EINVAL; in dma_stm32_configure()
436 if (stream->cyclic) { in dma_stm32_configure()
442 stream->source_periph = (stream->direction == PERIPHERAL_TO_MEMORY); in dma_stm32_configure()
445 int index = find_lsb_set(config->source_data_size) - 1; in dma_stm32_configure()
447 index = find_lsb_set(config->dest_data_size) - 1; in dma_stm32_configure()
451 DMA_InitStruct.MemBurst = stm32_dma_get_mburst(config, in dma_stm32_configure()
452 stream->source_periph); in dma_stm32_configure()
453 DMA_InitStruct.PeriphBurst = stm32_dma_get_pburst(config, in dma_stm32_configure()
454 stream->source_periph); in dma_stm32_configure()
457 if (config->channel_direction != MEMORY_TO_MEMORY) { in dma_stm32_configure()
458 if (config->dma_slot >= 8) { in dma_stm32_configure()
460 return -EINVAL; in dma_stm32_configure()
463 if (config->dma_slot >= 8) { in dma_stm32_configure()
465 config->dma_slot = 0; in dma_stm32_configure()
469 DMA_InitStruct.Channel = dma_stm32_slot_to_channel(config->dma_slot); in dma_stm32_configure()
473 config->head_block->fifo_mode_control); in dma_stm32_configure()
481 if (stream->source_periph) { in dma_stm32_configure()
482 DMA_InitStruct.NbData = config->head_block->block_size / in dma_stm32_configure()
483 config->source_data_size; in dma_stm32_configure()
485 DMA_InitStruct.NbData = config->head_block->block_size / in dma_stm32_configure()
486 config->dest_data_size; in dma_stm32_configure()
491 DMA_InitStruct.PeriphRequest = config->dma_slot; in dma_stm32_configure()
497 /* Enable Half-Transfer irq if circular mode is enabled */ in dma_stm32_configure()
498 if (stream->cyclic) { in dma_stm32_configure()
518 const struct dma_stm32_config *config = dev->config; in dma_stm32_reload() local
519 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_reload()
523 id = id - STM32_DMA_STREAM_OFFSET; in dma_stm32_reload()
525 if (id >= config->max_streams) { in dma_stm32_reload()
526 return -EINVAL; in dma_stm32_reload()
529 stream = &config->streams[id]; in dma_stm32_reload()
532 return -EBUSY; in dma_stm32_reload()
535 switch (stream->direction) { in dma_stm32_reload()
546 return -EINVAL; in dma_stm32_reload()
549 if (stream->source_periph) { in dma_stm32_reload()
551 size / stream->src_size); in dma_stm32_reload()
554 size / stream->dst_size); in dma_stm32_reload()
558 stream->busy = true; in dma_stm32_reload()
567 const struct dma_stm32_config *config = dev->config; in dma_stm32_start() local
568 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_start()
572 id = id - STM32_DMA_STREAM_OFFSET; in dma_stm32_start()
575 if (id >= config->max_streams) { in dma_stm32_start()
576 return -EINVAL; in dma_stm32_start()
585 stream = &config->streams[id]; in dma_stm32_start()
586 stream->busy = true; in dma_stm32_start()
596 const struct dma_stm32_config *config = dev->config; in dma_stm32_stop() local
597 struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET]; in dma_stm32_stop()
598 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_stop()
601 id = id - STM32_DMA_STREAM_OFFSET; in dma_stm32_stop()
603 if (id >= config->max_streams) { in dma_stm32_stop()
604 return -EINVAL; in dma_stm32_stop()
607 if (stream->hal_override) { in dma_stm32_stop()
608 stream->busy = false; in dma_stm32_stop()
630 stream->busy = false; in dma_stm32_stop()
637 const struct dma_stm32_config *config = dev->config; in dma_stm32_init() local
641 LOG_ERR("clock control device not ready"); in dma_stm32_init()
642 return -ENODEV; in dma_stm32_init()
646 (clock_control_subsys_t) &config->pclken) != 0) { in dma_stm32_init()
647 LOG_ERR("clock op failed\n"); in dma_stm32_init()
648 return -EIO; in dma_stm32_init()
651 config->config_irq(dev); in dma_stm32_init()
653 for (uint32_t i = 0; i < config->max_streams; i++) { in dma_stm32_init()
654 config->streams[i].busy = false; in dma_stm32_init()
656 /* Each further stream->mux_channel is fixed here */ in dma_stm32_init()
657 config->streams[i].mux_channel = i + config->offset; in dma_stm32_init()
661 ((struct dma_stm32_data *)dev->data)->dma_ctx.magic = 0; in dma_stm32_init()
662 ((struct dma_stm32_data *)dev->data)->dma_ctx.dma_channels = 0; in dma_stm32_init()
663 ((struct dma_stm32_data *)dev->data)->dma_ctx.atomic = 0; in dma_stm32_init()
671 const struct dma_stm32_config *config = dev->config; in dma_stm32_get_status() local
672 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_get_status()
676 id = id - STM32_DMA_STREAM_OFFSET; in dma_stm32_get_status()
677 if (id >= config->max_streams) { in dma_stm32_get_status()
678 return -EINVAL; in dma_stm32_get_status()
681 stream = &config->streams[id]; in dma_stm32_get_status()
682 stat->pending_length = LL_DMA_GetDataLength(dma, dma_stm32_id_to_stream(id)); in dma_stm32_get_status()
683 stat->dir = stream->direction; in dma_stm32_get_status()
684 stat->busy = stream->busy; in dma_stm32_get_status()
691 .config = dma_stm32_configure,