Lines Matching refs:__ASSERT
73 __ASSERT(channel_descriptor->CONFIG.TMD == 0, "Result of success: TMD set to zero"); in dma_si32_isr_handler()
74 __ASSERT(channel_descriptor->CONFIG.NCOUNT == 0, in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
101 __ASSERT(SI32_DMACTRL_0 == SI32_DMACTRL_0, "There is only one DMA controller"); in dma_si32_init()
102 __ASSERT(SI32_DMACTRL_A_get_number_of_channels(SI32_DMACTRL_0) >= CHANNEL_COUNT, in dma_si32_init()
205 __ASSERT(cfg->source_data_size == cfg->dest_data_size, in dma_si32_config()
366 __ASSERT(SI32_CLKCTRL_0->AHBCLKG.DMACEN, in dma_si32_start()
368 __ASSERT(SI32_DMACTRL_A_is_enabled(SI32_DMACTRL_0), "DMA controller must be enabled."); in dma_si32_start()
369 __ASSERT(SI32_DMACTRL_0->BASEPTR.U32 == (uintptr_t)channel_descriptors, in dma_si32_start()
371 __ASSERT(SI32_DMACTRL_A_is_primary_selected(SI32_DMACTRL_0, channel), in dma_si32_start()
373 __ASSERT(SI32_SCONFIG_0->CONFIG.FDMAEN, "Fast mode is recommened to be enabled."); in dma_si32_start()
374 __ASSERT(SI32_DMACTRL_0->CHSTATUS.U32 & BIT(channel), in dma_si32_start()
391 __ASSERT((SI32_DMACTRL_0->CHREQMSET.U32 & BIT(channel)), in dma_si32_start()
395 __ASSERT(!(SI32_DMACTRL_0->CHREQMSET.U32 & BIT(channel)), in dma_si32_start()