Lines Matching refs:bit
124 DMA_REGS->CHCTRLB.bit.LVL = config->channel_priority; in dma_sam0_config()
162 chcfg->CHPRILVL.bit.PRILVL = config->channel_priority; in dma_sam0_config()
199 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_BYTE_Val; in dma_sam0_config()
202 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_HWORD_Val; in dma_sam0_config()
205 btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_WORD_Val; in dma_sam0_config()
220 btctrl.bit.SRCINC = 1; in dma_sam0_config()
233 btctrl.bit.DSTINC = 1; in dma_sam0_config()
243 btctrl.bit.VALID = 1; in dma_sam0_config()
274 if (DMA_REGS->CHCTRLB.bit.TRIGSRC == 0) { in dma_sam0_start()
282 chcfg->CHCTRLA.bit.ENABLE = 1; in dma_sam0_start()
284 if (chcfg->CHCTRLA.bit.TRIGSRC == 0) { in dma_sam0_start()
307 chcfg->CHCTRLA.bit.ENABLE = 0; in dma_sam0_stop()
322 switch (desc->BTCTRL.bit.BEATSIZE) { in dma_sam0_reload()
336 if (desc->BTCTRL.bit.SRCINC) { in dma_sam0_reload()
342 if (desc->BTCTRL.bit.DSTINC) { in dma_sam0_reload()
380 switch (data->descriptors[channel].BTCTRL.bit.BEATSIZE) { in dma_sam0_get_status()
410 MCLK->AHBMASK.bit.DMAC_ = 1; in dma_sam0_init()
412 PM->AHBMASK.bit.DMAC_ = 1; in dma_sam0_init()
413 PM->APBBMASK.bit.DMAC_ = 1; in dma_sam0_init()