17 #define DMA_REGS	((Dmac *)DT_INST_REG_ADDR(0))  macro
35 	uint16_t pend = DMA_REGS->INTPEND.reg;  in dma_sam0_isr()
39 	DMA_REGS->INTPEND.reg = pend;  in dma_sam0_isr()
101 	DMA_REGS->CHID.reg = DMAC_CHID_ID(channel);  in dma_sam0_config()
102 	DMA_REGS->CHCTRLA.reg = 0;  in dma_sam0_config()
110 		DMA_REGS->CHCTRLB.reg = DMAC_CHCTRLB_TRIGACT_TRANSACTION |  in dma_sam0_config()
114 		DMA_REGS->CHCTRLB.reg = DMAC_CHCTRLB_TRIGACT_BEAT |  in dma_sam0_config()
124 	DMA_REGS->CHCTRLB.bit.LVL = config->channel_priority;  in dma_sam0_config()
127 	DMA_REGS->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;  in dma_sam0_config()
129 		DMA_REGS->CHINTENSET.reg = DMAC_CHINTENSET_TERR;  in dma_sam0_config()
131 		DMA_REGS->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;  in dma_sam0_config()
134 	DMA_REGS->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_TCMPL;  in dma_sam0_config()
137 	DmacChannel * chcfg = &DMA_REGS->Channel[channel];  in dma_sam0_config()
271 	DMA_REGS->CHID.reg = channel;  in dma_sam0_start()
272 	DMA_REGS->CHCTRLA.reg = DMAC_CHCTRLA_ENABLE;  in dma_sam0_start()
274 	if (DMA_REGS->CHCTRLB.bit.TRIGSRC == 0) {  in dma_sam0_start()
276 		DMA_REGS->SWTRIGCTRL.reg = 1U << channel;  in dma_sam0_start()
280 	DmacChannel * chcfg = &DMA_REGS->Channel[channel];  in dma_sam0_start()
286 		DMA_REGS->SWTRIGCTRL.reg = 1U << channel;  in dma_sam0_start()
302 	DMA_REGS->CHID.reg = channel;  in dma_sam0_stop()
303 	DMA_REGS->CHCTRLA.reg = 0;  in dma_sam0_stop()
305 	DmacChannel * chcfg = &DMA_REGS->Channel[channel];  in dma_sam0_stop()
369 	act = DMA_REGS->ACTIVE.reg;  in dma_sam0_get_status()
417 	DMA_REGS->BASEADDR.reg = (uintptr_t)&data->descriptors;  in dma_sam0_init()
418 	DMA_REGS->WRBADDR.reg = (uintptr_t)&data->descriptors_wb;  in dma_sam0_init()
421 	DMA_REGS->PRICTRL0.reg =  in dma_sam0_init()
426 	DMA_REGS->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0x0F);  in dma_sam0_init()