4  * SPDX-License-Identifier: Apache-2.0
37 /* used to generate an array of indexes for the channels */
41 /* used to generate an array of indexes for the channels - this is different
42  * from _EDMA_CHANNEL_INDEX_ARRAY because the number of channels is passed
43  * explicitly through dma-channels so no need to deduce it from the length
44  * of the valid-channels property.
64 /* used to declare a struct edma_channel by the non-explicit macro suite */
82 /* used to create an array of channel IDs via the valid-channels property */
87 /* used to create an array of channel IDs via the dma-channels property */
93  * dma-channels or valid-channels.
111  *	- in the context of cyclic buffers we introduce
112  *	the concepts of consumer and producer channels.
114  *	- a consumer channel is a channel for which the
119  *	- a producer channel is a channel for which the
124  *	- for consumer channels, each DMA interrupt will
129  *	- for producer channels, each DMA interrupt will
133  *	- to signal this, the ISR uses EDMA_CHAN_PRODUCE_CONSUME_A
135  *	consumer channels and "produce" data for
136  *	producer channels.
138  *	- since the upper layers using this driver need
140  *	(in the case of consumer channels) or consumed
141  *	data (in the case of producer channels) they can
144  *	- reload() uses EDMA_CHAN_PRODUCE_CONSUME_B which
145  *	for consumer channels will "produce" data and
146  *	"consume" data for producer channels, thus letting
151  *	producer channels).
153  *	- EDMA_CHAN_PRODUCE_CONSUME_B is just the opposite
155  *	data, the other will consume and vice-versa.
157  *	- all of this information is valid only in the
163 	((chan)->type == CHAN_TYPE_CONSUMER ?\
168 	((chan)->type == CHAN_TYPE_CONSUMER ?\
173 	(EDMA_ChannelRegRead((data)->hal_cfg, (chan)->id, EDMA_TCD_CH_CSR) &\
199 	/* type of the channel (PRODUCER/CONSUMER) - only applicable to cyclic
203 	/* argument passed to the user-defined DMA callback */
205 	/* user-defined callback, called at the end of a channel's interrupt
213 	/* cyclic buffer size - currently, this is set to head_block's size */
223 	struct edma_channel *channels;  member
232 	/* true if channels are contiguous. The channels may not be contiguous
233 	 * if the valid-channels property is used instead of dma-channels. This
243 	enum channel_state prev = chan->state;  in channel_allows_transition()
299 		return -EINVAL;  in get_transfer_type()
333 		chan->type = CHAN_TYPE_CONSUMER;  in edma_set_channel_type()
336 		chan->type = CHAN_TYPE_PRODUCER;  in edma_set_channel_type()
340 		return -ENOTSUP;  in edma_set_channel_type()
354  * This function is used in edma_isr() for CONSUMER channels to mark
357  * called in edma_isr()). For producer channels, this function is used
364 	if (bytes > chan->stat.pending_length) {  in edma_chan_cyclic_consume()
365 		return -EINVAL;  in edma_chan_cyclic_consume()
368 	chan->stat.read_position =  in edma_chan_cyclic_consume()
369 		(chan->stat.read_position + bytes) % chan->bsize;  in edma_chan_cyclic_consume()
371 	if (chan->stat.read_position > chan->stat.write_position) {  in edma_chan_cyclic_consume()
372 		chan->stat.free = chan->stat.read_position -  in edma_chan_cyclic_consume()
373 			chan->stat.write_position;  in edma_chan_cyclic_consume()
374 	} else if (chan->stat.read_position == chan->stat.write_position) {  in edma_chan_cyclic_consume()
375 		chan->stat.free = chan->bsize;  in edma_chan_cyclic_consume()
377 		chan->stat.free = chan->bsize -  in edma_chan_cyclic_consume()
378 			(chan->stat.write_position - chan->stat.read_position);  in edma_chan_cyclic_consume()
381 	chan->stat.pending_length = chan->bsize - chan->stat.free;  in edma_chan_cyclic_consume()
393  * This function is used in edma_isr() for PRODUCER channels to mark
396  * called in edma_isr()). For consumer channels, this function is used
403 	if (bytes > chan->stat.free) {  in edma_chan_cyclic_produce()
404 		return -EINVAL;  in edma_chan_cyclic_produce()
407 	chan->stat.write_position =  in edma_chan_cyclic_produce()
408 		(chan->stat.write_position + bytes) % chan->bsize;  in edma_chan_cyclic_produce()
410 	if (chan->stat.write_position > chan->stat.read_position) {  in edma_chan_cyclic_produce()
411 		chan->stat.pending_length = chan->stat.write_position -  in edma_chan_cyclic_produce()
412 			chan->stat.read_position;  in edma_chan_cyclic_produce()
413 	} else if (chan->stat.write_position == chan->stat.read_position) {  in edma_chan_cyclic_produce()
414 		chan->stat.pending_length = chan->bsize;  in edma_chan_cyclic_produce()
416 		chan->stat.pending_length = chan->bsize -  in edma_chan_cyclic_produce()
417 			(chan->stat.read_position - chan->stat.write_position);  in edma_chan_cyclic_produce()
420 	chan->stat.free = chan->bsize - chan->stat.pending_length;  in edma_chan_cyclic_produce()
433 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_CSR));  in edma_dump_channel_registers()
435 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_ES));  in edma_dump_channel_registers()
437 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_INT));  in edma_dump_channel_registers()
439 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_SBR));  in edma_dump_channel_registers()
441 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_PRI));  in edma_dump_channel_registers()
443 	if (EDMA_HAS_MUX(data->hal_cfg)) {  in edma_dump_channel_registers()
444 		if (data->hal_cfg->flags & EDMA_HAS_MP_MUX_FLAG) {  in edma_dump_channel_registers()
450 		LOG_DBG("CH_MUX: 0x%x", EDMA_ChannelRegRead(data->hal_cfg, chan_id, mux_reg));  in edma_dump_channel_registers()
454 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_SADDR));  in edma_dump_channel_registers()
456 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_SOFF));  in edma_dump_channel_registers()
458 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_ATTR));  in edma_dump_channel_registers()
460 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_NBYTES));  in edma_dump_channel_registers()
462 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA));  in edma_dump_channel_registers()
464 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_DADDR));  in edma_dump_channel_registers()
466 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_DOFF));  in edma_dump_channel_registers()
468 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CITER));  in edma_dump_channel_registers()
470 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA));  in edma_dump_channel_registers()
472 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CSR));  in edma_dump_channel_registers()
474 		EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_BITER));  in edma_dump_channel_registers()
487 		switch (dma_cfg->head_block->source_addr_adj) {  in set_slast_dlast()
489 			slast = (int32_t)dma_cfg->head_block->block_size;  in set_slast_dlast()
492 			slast = (-1) * (int32_t)dma_cfg->head_block->block_size;  in set_slast_dlast()
496 				dma_cfg->head_block->source_addr_adj);  in set_slast_dlast()
497 			return -EINVAL;  in set_slast_dlast()
504 		switch (dma_cfg->head_block->dest_addr_adj) {  in set_slast_dlast()
506 			dlast = (int32_t)dma_cfg->head_block->block_size;  in set_slast_dlast()
509 			dlast = (-1) * (int32_t)dma_cfg->head_block->block_size;  in set_slast_dlast()
513 				dma_cfg->head_block->dest_addr_adj);  in set_slast_dlast()
514 			return -EINVAL;  in set_slast_dlast()
522 	EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA, slast);  in set_slast_dlast()
523 	EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA, dlast);  in set_slast_dlast()
525 	if (data->hal_cfg->flags & EDMA_HAS_64BIT_TCD_FLAG) {  in set_slast_dlast()
526 		EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA_HIGH,  in set_slast_dlast()
528 		EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA_HIGH,  in set_slast_dlast()
544 		return -EINVAL;  in to_std_error()
546 		return -EBUSY;  in to_std_error()
549 		return -EINVAL;  in to_std_error()