235 	uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel);  in dma_mcux_edma_irq_handler()  local
236 	uint32_t flag = EDMA_GetChannelStatusFlags(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_irq_handler()
261 	uint32_t hw_channel;  in dma_mcux_edma_error_irq_handler()  local
265 			hw_channel = dma_mcux_edma_add_channel_gap(dev, i);  in dma_mcux_edma_error_irq_handler()
266 			flag = EDMA_GetChannelStatusFlags(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_error_irq_handler()
267 			EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel, 0xFFFFFFFF);  in dma_mcux_edma_error_irq_handler()
270 			LOG_INF("channel %d error status is 0x%x", hw_channel, flag);  in dma_mcux_edma_error_irq_handler()
293 	uint32_t hw_channel;  in dma_mcux_edma_configure()  local
309 	hw_channel = dma_mcux_edma_add_channel_gap(dev, channel);  in dma_mcux_edma_configure()
388 	EDMA_ResetChannel(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_configure()
389 	EDMA_CreateHandle(p_handle, DEV_BASE(dev), hw_channel);  in dma_mcux_edma_configure()
394 	EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0);  in dma_mcux_edma_configure()
395 	EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot);  in dma_mcux_edma_configure()
399 	EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable);  in dma_mcux_edma_configure()
462 			EDMA_InstallTCD(p_handle->base, hw_channel,  in dma_mcux_edma_configure()
507 		LOG_DBG("DMA TCD CSR 0x%x", EDMA_HW_TCD_CSR(dev, hw_channel));  in dma_mcux_edma_configure()
558 	uint32_t hw_channel;  in dma_mcux_edma_stop()  local
560 	hw_channel = dma_mcux_edma_add_channel_gap(dev, channel);  in dma_mcux_edma_stop()
569 	EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel,  in dma_mcux_edma_stop()
572 	EDMA_ResetChannel(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_stop()
751 	uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel);  in dma_mcux_edma_get_status()  local
759 			EDMA_GetRemainingMajorLoopCount(DEV_BASE(dev), hw_channel) *  in dma_mcux_edma_get_status()
777 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);  in dma_mcux_edma_get_status()
778 	LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR);  in dma_mcux_edma_get_status()
779 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);  in dma_mcux_edma_get_status()
780 	LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT);  in dma_mcux_edma_get_status()
781 	LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR);  in dma_mcux_edma_get_status()
789 	LOG_DBG("data csr is 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR);  in dma_mcux_edma_get_status()