119 #define DEV_BASE(dev) ((DMA_Type *)DEV_CFG(dev)->base)  macro
156 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].SADDR)
157 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].DADDR)
158 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->TCD[ch].BITER_ELINKNO)
159 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->TCD[ch].CITER_ELINKNO)
160 #define EDMA_HW_TCD_CSR(dev, ch)   (DEV_BASE(dev)->TCD[ch].CSR)
162 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
163 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
164 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
165 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
166 #define EDMA_HW_TCD_CSR(dev, ch)   (DEV_BASE(dev)->CH[ch].TCD_CSR)
236 	uint32_t flag = EDMA_GetChannelStatusFlags(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_irq_handler()
248 		EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, 0xFFFFFFFF);  in dma_mcux_edma_irq_handler()
266 			flag = EDMA_GetChannelStatusFlags(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_error_irq_handler()
267 			EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel, 0xFFFFFFFF);  in dma_mcux_edma_error_irq_handler()
388 	EDMA_ResetChannel(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_configure()
389 	EDMA_CreateHandle(p_handle, DEV_BASE(dev), hw_channel);  in dma_mcux_edma_configure()
394 	EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0);  in dma_mcux_edma_configure()
395 	EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot);  in dma_mcux_edma_configure()
399 	EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable);  in dma_mcux_edma_configure()
512 		EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MajorLink,  in dma_mcux_edma_configure()
517 		EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MinorLink,  in dma_mcux_edma_configure()
548 	LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR);  in dma_mcux_edma_start()
569 	EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel,  in dma_mcux_edma_stop()
572 	EDMA_ResetChannel(DEV_BASE(dev), hw_channel);  in dma_mcux_edma_stop()
660 		EDMA_DisableChannelRequest(DEV_BASE(dev), channel);  in dma_mcux_edma_reload()
691 				EDMA_EnableAutoStopRequest(DEV_BASE(dev), channel, false);  in dma_mcux_edma_reload()
701 		EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, kEDMA_DoneFlag);  in dma_mcux_edma_reload()
707 		EDMA_EnableChannelRequest(DEV_BASE(dev), channel);  in dma_mcux_edma_reload()
759 			EDMA_GetRemainingMajorLoopCount(DEV_BASE(dev), hw_channel) *  in dma_mcux_edma_get_status()
775 	LOG_DBG("DMA MP_CSR 0x%x",  DEV_BASE(dev)->MP_CSR);  in dma_mcux_edma_get_status()
776 	LOG_DBG("DMA MP_ES 0x%x",   DEV_BASE(dev)->MP_ES);  in dma_mcux_edma_get_status()
777 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);  in dma_mcux_edma_get_status()
778 	LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR);  in dma_mcux_edma_get_status()
779 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);  in dma_mcux_edma_get_status()
780 	LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT);  in dma_mcux_edma_get_status()
781 	LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR);  in dma_mcux_edma_get_status()
783 	LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR);  in dma_mcux_edma_get_status()
784 	LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT);  in dma_mcux_edma_get_status()
785 	LOG_DBG("DMA ERQ 0x%x", DEV_BASE(dev)->ERQ);  in dma_mcux_edma_get_status()
786 	LOG_DBG("DMA ES 0x%x", DEV_BASE(dev)->ES);  in dma_mcux_edma_get_status()
787 	LOG_DBG("DMA ERR 0x%x", DEV_BASE(dev)->ERR);  in dma_mcux_edma_get_status()
788 	LOG_DBG("DMA HRS 0x%x", DEV_BASE(dev)->HRS);  in dma_mcux_edma_get_status()
789 	LOG_DBG("data csr is 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR);  in dma_mcux_edma_get_status()
836 	EDMA_Init(DEV_BASE(dev), &userConfig);  in dma_mcux_edma_init()
839 	EDMA_EnableAllChannelLink(DEV_BASE(dev), true);  in dma_mcux_edma_init()