Lines Matching +full:channel +full:- +full:gap
2 * Copyright 2020-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
117 ((const struct dma_mcux_edma_config *const)dev->config)
118 #define DEV_DATA(dev) ((struct dma_mcux_edma_data *)dev->data)
119 #define DEV_BASE(dev) ((DMA_Type *)DEV_CFG(dev)->base)
122 ((struct call_back *)(&(DEV_DATA(dev)->data_cb[ch])))
125 ((edma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->edma_handle)))
128 #define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx])
129 #define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux)
132 (ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->dmamux_reg_offset)
137 #define EDMA_TCD_SADDR(tcd, flag) ((tcd)->SADDR)
138 #define EDMA_TCD_DADDR(tcd, flag) ((tcd)->DADDR)
139 #define EDMA_TCD_BITER(tcd, flag) ((tcd)->BITER)
140 #define EDMA_TCD_CITER(tcd, flag) ((tcd)->CITER)
141 #define EDMA_TCD_CSR(tcd, flag) ((tcd)->CSR)
142 #define EDMA_TCD_DLAST_SGA(tcd, flag) ((tcd)->DLAST_SGA)
156 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].SADDR)
157 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].DADDR)
158 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->TCD[ch].BITER_ELINKNO)
159 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->TCD[ch].CITER_ELINKNO)
160 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->TCD[ch].CSR)
162 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
163 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
164 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
165 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
166 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CSR)
170 * The hardware channel (takes the gap into account) is used when access DMA registers.
171 * For data structures in the shim driver still use the primitive channel.
174 uint32_t channel) in dma_mcux_edma_add_channel_gap() argument
179 return (channel < config->channel_gap[0]) ? channel : in dma_mcux_edma_add_channel_gap()
180 (channel + 1 + config->channel_gap[1] - config->channel_gap[0]); in dma_mcux_edma_add_channel_gap()
183 return channel; in dma_mcux_edma_add_channel_gap()
188 uint32_t channel) in dma_mcux_edma_remove_channel_gap() argument
193 return (channel < config->channel_gap[0]) ? channel : in dma_mcux_edma_remove_channel_gap()
194 (channel + config->channel_gap[0] - config->channel_gap[1] - 1); in dma_mcux_edma_remove_channel_gap()
197 return channel; in dma_mcux_edma_remove_channel_gap()
215 int ret = -EIO; in nxp_edma_callback()
217 uint32_t channel = dma_mcux_edma_remove_channel_gap(data->dev, handle->channel); in nxp_edma_callback() local
219 if (data->transfer_settings.cyclic) { in nxp_edma_callback()
220 data->transfer_settings.empty_tcds++; in nxp_edma_callback()
222 data->busy = 1; in nxp_edma_callback()
226 data->busy = (handle->tcdPool != NULL) && (handle->tcdUsed > 0); in nxp_edma_callback()
230 data->dma_callback(data->dev, data->user_data, channel, ret); in nxp_edma_callback()
233 static void dma_mcux_edma_irq_handler(const struct device *dev, uint32_t channel) in dma_mcux_edma_irq_handler() argument
235 uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); in dma_mcux_edma_irq_handler()
241 EDMA_HandleIRQ(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_irq_handler()
246 /* Channel shares the same irq for error and transfer complete */ in dma_mcux_edma_irq_handler()
248 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, 0xFFFFFFFF); in dma_mcux_edma_irq_handler()
249 EDMA_AbortTransfer(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_irq_handler()
250 DEV_CHANNEL_DATA(dev, channel)->busy = false; in dma_mcux_edma_irq_handler()
251 LOG_INF("channel %d error status is 0x%x", channel, flag); in dma_mcux_edma_irq_handler()
263 for (i = 0; i < DEV_CFG(dev)->dma_channels; i++) { in dma_mcux_edma_error_irq_handler()
264 if (DEV_CHANNEL_DATA(dev, i)->busy) { in dma_mcux_edma_error_irq_handler()
269 DEV_CHANNEL_DATA(dev, i)->busy = false; in dma_mcux_edma_error_irq_handler()
270 LOG_INF("channel %d error status is 0x%x", hw_channel, flag); in dma_mcux_edma_error_irq_handler()
280 /* Configure a channel */
281 static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, in dma_mcux_edma_configure() argument
286 return -EINVAL; in dma_mcux_edma_configure()
289 edma_handle_t *p_handle = DEV_EDMA_HANDLE(dev, channel); in dma_mcux_edma_configure()
290 struct call_back *data = DEV_CHANNEL_DATA(dev, channel); in dma_mcux_edma_configure()
291 struct dma_block_config *block_config = config->head_block; in dma_mcux_edma_configure()
292 uint32_t slot = config->dma_slot; in dma_mcux_edma_configure()
299 if (slot >= DEV_CFG(dev)->dma_requests) { in dma_mcux_edma_configure()
301 return -ENOTSUP; in dma_mcux_edma_configure()
304 if (channel >= DEV_CFG(dev)->dma_channels) { in dma_mcux_edma_configure()
305 LOG_ERR("out of DMA channel %d", channel); in dma_mcux_edma_configure()
306 return -EINVAL; in dma_mcux_edma_configure()
309 hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); in dma_mcux_edma_configure()
313 dmamux_idx = DEV_DMAMUX_IDX(dev, channel); in dma_mcux_edma_configure()
314 dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); in dma_mcux_edma_configure()
316 data->transfer_settings.valid = false; in dma_mcux_edma_configure()
318 switch (config->channel_direction) { in dma_mcux_edma_configure()
333 return -EINVAL; in dma_mcux_edma_configure()
336 if (!data_size_valid(config->source_data_size)) { in dma_mcux_edma_configure()
337 LOG_ERR("Source unit size error, %d", config->source_data_size); in dma_mcux_edma_configure()
338 return -EINVAL; in dma_mcux_edma_configure()
341 if (!data_size_valid(config->dest_data_size)) { in dma_mcux_edma_configure()
342 LOG_ERR("Dest unit size error, %d", config->dest_data_size); in dma_mcux_edma_configure()
343 return -EINVAL; in dma_mcux_edma_configure()
346 if (block_config->source_gather_en || block_config->dest_scatter_en) { in dma_mcux_edma_configure()
347 if (config->block_count > CONFIG_DMA_TCD_QUEUE_SIZE) { in dma_mcux_edma_configure()
348 LOG_ERR("please config DMA_TCD_QUEUE_SIZE as %d", config->block_count); in dma_mcux_edma_configure()
349 return -EINVAL; in dma_mcux_edma_configure()
353 data->transfer_settings.source_data_size = config->source_data_size; in dma_mcux_edma_configure()
354 data->transfer_settings.dest_data_size = config->dest_data_size; in dma_mcux_edma_configure()
355 data->transfer_settings.source_burst_length = config->source_burst_length; in dma_mcux_edma_configure()
356 data->transfer_settings.dest_burst_length = config->dest_burst_length; in dma_mcux_edma_configure()
357 data->transfer_settings.direction = config->channel_direction; in dma_mcux_edma_configure()
358 data->transfer_settings.transfer_type = transfer_type; in dma_mcux_edma_configure()
359 data->transfer_settings.valid = true; in dma_mcux_edma_configure()
360 data->transfer_settings.cyclic = config->cyclic; in dma_mcux_edma_configure()
362 /* Lock and page in the channel configuration */ in dma_mcux_edma_configure()
368 if (config->source_handshake || config->dest_handshake || in dma_mcux_edma_configure()
370 /*software trigger make the channel always on*/ in dma_mcux_edma_configure()
380 /* dam_imx_rt_set_channel_priority(dev, channel, config); */ in dma_mcux_edma_configure()
385 if (data->busy) { in dma_mcux_edma_configure()
393 /* First release any peripheral previously associated with this channel */ in dma_mcux_edma_configure()
398 LOG_DBG("channel is %d", channel); in dma_mcux_edma_configure()
403 memset(&DEV_CFG(dev)->tcdpool[channel][i], 0, in dma_mcux_edma_configure()
404 sizeof(DEV_CFG(dev)->tcdpool[channel][i])); in dma_mcux_edma_configure()
407 if (block_config->source_gather_en || block_config->dest_scatter_en) { in dma_mcux_edma_configure()
408 if (config->cyclic) { in dma_mcux_edma_configure()
410 data->transfer_settings.write_idx = 0; in dma_mcux_edma_configure()
411 data->transfer_settings.empty_tcds = CONFIG_DMA_TCD_QUEUE_SIZE; in dma_mcux_edma_configure()
414 &data->transferConfig, (void *)block_config->source_address, in dma_mcux_edma_configure()
415 config->source_data_size, (void *)block_config->dest_address, in dma_mcux_edma_configure()
416 config->dest_data_size, config->source_burst_length, in dma_mcux_edma_configure()
417 block_config->block_size, transfer_type); in dma_mcux_edma_configure()
422 &DEV_CFG(dev)->tcdpool[channel][i], &data->transferConfig, in dma_mcux_edma_configure()
423 &DEV_CFG(dev)->tcdpool[channel][(i + 1) % in dma_mcux_edma_configure()
427 EDMA_TcdEnableInterrupts(&DEV_CFG(dev)->tcdpool[channel][i], in dma_mcux_edma_configure()
432 while (block_config != NULL && data->transfer_settings.empty_tcds > 0) { in dma_mcux_edma_configure()
433 tcd = &(DEV_CFG(dev)->tcdpool[channel] in dma_mcux_edma_configure()
434 [data->transfer_settings.write_idx]); in dma_mcux_edma_configure()
436 EDMA_TCD_SADDR(tcd, kEDMA_EDMA4Flag) = block_config->source_address; in dma_mcux_edma_configure()
437 EDMA_TCD_DADDR(tcd, kEDMA_EDMA4Flag) = block_config->dest_address; in dma_mcux_edma_configure()
439 block_config->block_size / config->source_data_size; in dma_mcux_edma_configure()
441 block_config->block_size / config->source_data_size; in dma_mcux_edma_configure()
443 if (block_config->next_block == NULL) { in dma_mcux_edma_configure()
449 data->transfer_settings.write_idx = in dma_mcux_edma_configure()
450 (data->transfer_settings.write_idx + 1) % in dma_mcux_edma_configure()
452 data->transfer_settings.empty_tcds--; in dma_mcux_edma_configure()
453 block_config = block_config->next_block; in dma_mcux_edma_configure()
456 if (block_config != NULL && data->transfer_settings.empty_tcds == 0) { in dma_mcux_edma_configure()
459 ret = -ENOBUFS; in dma_mcux_edma_configure()
462 EDMA_InstallTCD(p_handle->base, hw_channel, in dma_mcux_edma_configure()
463 &DEV_CFG(dev)->tcdpool[channel][0]); in dma_mcux_edma_configure()
467 EDMA_InstallTCDMemory(p_handle, DEV_CFG(dev)->tcdpool[channel], in dma_mcux_edma_configure()
471 EDMA_PrepareTransfer(&(data->transferConfig), in dma_mcux_edma_configure()
472 (void *)block_config->source_address, in dma_mcux_edma_configure()
473 config->source_data_size, in dma_mcux_edma_configure()
474 (void *)block_config->dest_address, in dma_mcux_edma_configure()
475 config->dest_data_size, in dma_mcux_edma_configure()
476 config->source_burst_length, in dma_mcux_edma_configure()
477 block_config->block_size, transfer_type); in dma_mcux_edma_configure()
480 EDMA_SubmitTransfer(p_handle, &(data->transferConfig)); in dma_mcux_edma_configure()
484 ret = -EFAULT; in dma_mcux_edma_configure()
486 block_config = block_config->next_block; in dma_mcux_edma_configure()
491 LOG_DBG("block size is: %d", block_config->block_size); in dma_mcux_edma_configure()
492 EDMA_PrepareTransfer(&(data->transferConfig), in dma_mcux_edma_configure()
493 (void *)block_config->source_address, in dma_mcux_edma_configure()
494 config->source_data_size, in dma_mcux_edma_configure()
495 (void *)block_config->dest_address, in dma_mcux_edma_configure()
496 config->dest_data_size, in dma_mcux_edma_configure()
497 config->source_burst_length, in dma_mcux_edma_configure()
498 block_config->block_size, transfer_type); in dma_mcux_edma_configure()
501 EDMA_SubmitTransfer(p_handle, &(data->transferConfig)); in dma_mcux_edma_configure()
504 ret = -EFAULT; in dma_mcux_edma_configure()
510 if (config->dest_chaining_en) { in dma_mcux_edma_configure()
511 LOG_DBG("link major channel %d", config->linked_channel); in dma_mcux_edma_configure()
512 EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MajorLink, in dma_mcux_edma_configure()
513 config->linked_channel); in dma_mcux_edma_configure()
515 if (config->source_chaining_en) { in dma_mcux_edma_configure()
516 LOG_DBG("link minor channel %d", config->linked_channel); in dma_mcux_edma_configure()
517 EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MinorLink, in dma_mcux_edma_configure()
518 config->linked_channel); in dma_mcux_edma_configure()
521 data->busy = false; in dma_mcux_edma_configure()
522 if (config->dma_callback) { in dma_mcux_edma_configure()
523 LOG_DBG("INSTALL call back on channel %d", channel); in dma_mcux_edma_configure()
524 data->user_data = config->user_data; in dma_mcux_edma_configure()
525 data->dma_callback = config->dma_callback; in dma_mcux_edma_configure()
526 data->dev = dev; in dma_mcux_edma_configure()
534 static int dma_mcux_edma_start(const struct device *dev, uint32_t channel) in dma_mcux_edma_start() argument
536 struct call_back *data = DEV_CHANNEL_DATA(dev, channel); in dma_mcux_edma_start()
541 uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); in dma_mcux_edma_start()
542 uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); in dma_mcux_edma_start()
544 LOG_DBG("DMAMUX CHCFG 0x%x", DEV_DMAMUX_BASE(dev, dmamux_idx)->CHCFG[dmamux_channel]); in dma_mcux_edma_start()
548 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_start()
550 data->busy = true; in dma_mcux_edma_start()
551 EDMA_StartTransfer(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_start()
555 static int dma_mcux_edma_stop(const struct device *dev, uint32_t channel) in dma_mcux_edma_stop() argument
560 hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); in dma_mcux_edma_stop()
562 data->data_cb[channel].transfer_settings.valid = false; in dma_mcux_edma_stop()
564 if (!data->data_cb[channel].busy) { in dma_mcux_edma_stop()
568 EDMA_AbortTransfer(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_stop()
573 data->data_cb[channel].busy = false; in dma_mcux_edma_stop()
577 static int dma_mcux_edma_suspend(const struct device *dev, uint32_t channel) in dma_mcux_edma_suspend() argument
579 struct call_back *data = DEV_CHANNEL_DATA(dev, channel); in dma_mcux_edma_suspend()
581 if (!data->busy) { in dma_mcux_edma_suspend()
582 return -EINVAL; in dma_mcux_edma_suspend()
584 EDMA_StopTransfer(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_suspend()
588 static int dma_mcux_edma_resume(const struct device *dev, uint32_t channel) in dma_mcux_edma_resume() argument
590 struct call_back *data = DEV_CHANNEL_DATA(dev, channel); in dma_mcux_edma_resume()
592 if (!data->busy) { in dma_mcux_edma_resume()
593 return -EINVAL; in dma_mcux_edma_resume()
595 EDMA_StartTransfer(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_resume()
599 static void dma_mcux_edma_update_hw_tcd(const struct device *dev, uint32_t channel, uint32_t src, in dma_mcux_edma_update_hw_tcd() argument
602 EDMA_HW_TCD_SADDR(dev, channel) = src; in dma_mcux_edma_update_hw_tcd()
603 EDMA_HW_TCD_DADDR(dev, channel) = dst; in dma_mcux_edma_update_hw_tcd()
604 EDMA_HW_TCD_BITER(dev, channel) = size; in dma_mcux_edma_update_hw_tcd()
605 EDMA_HW_TCD_CITER(dev, channel) = size; in dma_mcux_edma_update_hw_tcd()
606 EDMA_HW_TCD_CSR(dev, channel) |= DMA_CSR_DREQ(1U); in dma_mcux_edma_update_hw_tcd()
609 static int dma_mcux_edma_reload(const struct device *dev, uint32_t channel, in dma_mcux_edma_reload() argument
612 struct call_back *data = DEV_CHANNEL_DATA(dev, channel); in dma_mcux_edma_reload()
618 /* Lock the channel configuration */ in dma_mcux_edma_reload()
622 if (!data->transfer_settings.valid) { in dma_mcux_edma_reload()
624 ret = -EFAULT; in dma_mcux_edma_reload()
628 if (data->transfer_settings.cyclic) { in dma_mcux_edma_reload()
629 if (data->transfer_settings.empty_tcds == 0) { in dma_mcux_edma_reload()
631 ret = -ENOBUFS; in dma_mcux_edma_reload()
636 size = size / data->transfer_settings.dest_data_size; in dma_mcux_edma_reload()
639 pre_idx = data->transfer_settings.write_idx - 1; in dma_mcux_edma_reload()
641 pre_idx = CONFIG_DMA_TCD_QUEUE_SIZE - 1; in dma_mcux_edma_reload()
644 tcd = &(DEV_CFG(dev)->tcdpool[channel][data->transfer_settings.write_idx]); in dma_mcux_edma_reload()
645 pre_tcd = &(DEV_CFG(dev)->tcdpool[channel][pre_idx]); in dma_mcux_edma_reload()
660 EDMA_DisableChannelRequest(DEV_BASE(dev), channel); in dma_mcux_edma_reload()
666 while (EDMA_HW_TCD_CSR(dev, channel) & EDMA_HW_TCD_CH_ACTIVE_MASK) { in dma_mcux_edma_reload()
671 hw_id = EDMA_GetNextTCDAddress(DEV_EDMA_HANDLE(dev, channel)); in dma_mcux_edma_reload()
672 if (data->transfer_settings.empty_tcds >= CONFIG_DMA_TCD_QUEUE_SIZE || in dma_mcux_edma_reload()
677 dma_mcux_edma_update_hw_tcd(dev, channel, src, dst, size); in dma_mcux_edma_reload()
686 if (data->transfer_settings.empty_tcds == CONFIG_DMA_TCD_QUEUE_SIZE - 1 || in dma_mcux_edma_reload()
691 EDMA_EnableAutoStopRequest(DEV_BASE(dev), channel, false); in dma_mcux_edma_reload()
701 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, kEDMA_DoneFlag); in dma_mcux_edma_reload()
702 EDMA_HW_TCD_CSR(dev, channel) |= DMA_CSR_ESG_MASK; in dma_mcux_edma_reload()
707 EDMA_EnableChannelRequest(DEV_BASE(dev), channel); in dma_mcux_edma_reload()
710 data->transfer_settings.write_idx = in dma_mcux_edma_reload()
711 (data->transfer_settings.write_idx + 1) % CONFIG_DMA_TCD_QUEUE_SIZE; in dma_mcux_edma_reload()
712 data->transfer_settings.empty_tcds--; in dma_mcux_edma_reload()
714 LOG_DBG("w_idx:%d no:%d(ch:%d)", data->transfer_settings.write_idx, in dma_mcux_edma_reload()
715 data->transfer_settings.empty_tcds, channel); in dma_mcux_edma_reload()
722 if (data->busy && data->edma_handle.tcdPool == NULL) { in dma_mcux_edma_reload()
724 ret = -EBUSY; in dma_mcux_edma_reload()
728 EDMA_PrepareTransfer(&(data->transferConfig), (void *)src, in dma_mcux_edma_reload()
729 data->transfer_settings.source_data_size, (void *)dst, in dma_mcux_edma_reload()
730 data->transfer_settings.dest_data_size, in dma_mcux_edma_reload()
731 data->transfer_settings.source_burst_length, size, in dma_mcux_edma_reload()
732 data->transfer_settings.transfer_type); in dma_mcux_edma_reload()
735 EDMA_SubmitTransfer(DEV_EDMA_HANDLE(dev, channel), &(data->transferConfig)); in dma_mcux_edma_reload()
739 ret = -EFAULT; in dma_mcux_edma_reload()
748 static int dma_mcux_edma_get_status(const struct device *dev, uint32_t channel, in dma_mcux_edma_get_status() argument
751 uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); in dma_mcux_edma_get_status()
753 if (DEV_CHANNEL_DATA(dev, channel)->busy) { in dma_mcux_edma_get_status()
754 status->busy = true; in dma_mcux_edma_get_status()
758 status->pending_length = in dma_mcux_edma_get_status()
760 DEV_CHANNEL_DATA(dev, channel)->transfer_settings.source_data_size; in dma_mcux_edma_get_status()
762 status->busy = false; in dma_mcux_edma_get_status()
763 status->pending_length = 0; in dma_mcux_edma_get_status()
765 status->dir = DEV_CHANNEL_DATA(dev, channel)->transfer_settings.direction; in dma_mcux_edma_get_status()
768 uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); in dma_mcux_edma_get_status()
769 uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); in dma_mcux_edma_get_status()
771 LOG_DBG("DMAMUX CHCFG 0x%x", DEV_DMAMUX_BASE(dev, dmamux_idx)->CHCFG[dmamux_channel]); in dma_mcux_edma_get_status()
775 LOG_DBG("DMA MP_CSR 0x%x", DEV_BASE(dev)->MP_CSR); in dma_mcux_edma_get_status()
776 LOG_DBG("DMA MP_ES 0x%x", DEV_BASE(dev)->MP_ES); in dma_mcux_edma_get_status()
777 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
778 LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR); in dma_mcux_edma_get_status()
779 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
780 LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT); in dma_mcux_edma_get_status()
781 LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR); in dma_mcux_edma_get_status()
783 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_get_status()
784 LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT); in dma_mcux_edma_get_status()
785 LOG_DBG("DMA ERQ 0x%x", DEV_BASE(dev)->ERQ); in dma_mcux_edma_get_status()
786 LOG_DBG("DMA ES 0x%x", DEV_BASE(dev)->ES); in dma_mcux_edma_get_status()
787 LOG_DBG("DMA ERR 0x%x", DEV_BASE(dev)->ERR); in dma_mcux_edma_get_status()
788 LOG_DBG("DMA HRS 0x%x", DEV_BASE(dev)->HRS); in dma_mcux_edma_get_status()
789 LOG_DBG("data csr is 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR); in dma_mcux_edma_get_status()
820 const struct dma_mcux_edma_config *config = dev->config; in dma_mcux_edma_init()
821 struct dma_mcux_edma_data *data = dev->data; in dma_mcux_edma_init()
830 for (i = 0; i < config->dma_channels / config->channels_per_mux; i++) { in dma_mcux_edma_init()
838 /* Channel linking available and will be controlled by each channel's link settings */ in dma_mcux_edma_init()
841 config->irq_config_func(dev); in dma_mcux_edma_init()
842 data->dma_ctx.magic = DMA_MAGIC; in dma_mcux_edma_init()
843 data->dma_ctx.dma_channels = config->dma_channels; in dma_mcux_edma_init()
844 data->dma_ctx.atomic = data->channels_atomic; in dma_mcux_edma_init()