194 static void xec_dma_chan_clr(struct dma_xec_chan_regs * const chregs,  in xec_dma_chan_clr()  argument
197 	chregs->actv = 0;  in xec_dma_chan_clr()
198 	chregs->control = 0;  in xec_dma_chan_clr()
199 	chregs->mem_addr = 0;  in xec_dma_chan_clr()
200 	chregs->mem_addr_end = 0;  in xec_dma_chan_clr()
201 	chregs->dev_addr = 0;  in xec_dma_chan_clr()
202 	chregs->control = 0;  in xec_dma_chan_clr()
203 	chregs->ienable = 0;  in xec_dma_chan_clr()
204 	chregs->istatus = 0xffu;  in xec_dma_chan_clr()
353 	struct dma_xec_chan_regs * const chregs = xec_chan_regs(regs, channel);  in dma_xec_configure()  local
359 	xec_dma_chan_clr(chregs, info);  in dma_xec_configure()
431 	chregs->actv &= ~BIT(XEC_DMA_CHAN_ACTV_EN_POS);  in dma_xec_configure()
432 	chregs->mem_addr = mstart;  in dma_xec_configure()
433 	chregs->mem_addr_end = mend;  in dma_xec_configure()
434 	chregs->dev_addr = dstart;  in dma_xec_configure()
436 	chregs->control = ctrl;  in dma_xec_configure()
437 	chregs->ienable = BIT(XEC_DMA_CHAN_IES_BERR_POS) | BIT(XEC_DMA_CHAN_IES_DONE_POS);  in dma_xec_configure()
438 	chregs->actv |= BIT(XEC_DMA_CHAN_ACTV_EN_POS);  in dma_xec_configure()
464 	struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel);  in dma_xec_reload()  local
466 	if (chregs->control & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS)) {  in dma_xec_reload()
470 	ctrl = chregs->control & ~(BIT(XEC_DMA_CHAN_CTRL_HWFL_RUN_POS)  in dma_xec_reload()
472 	chregs->ienable = 0;  in dma_xec_reload()
473 	chregs->control = 0;  in dma_xec_reload()
474 	chregs->istatus = 0xffu;  in dma_xec_reload()
488 	chregs->mem_addr = chdata->mstart;  in dma_xec_reload()
489 	chregs->mem_addr_end = chdata->mend;  in dma_xec_reload()
490 	chregs->dev_addr = chdata->dstart;  in dma_xec_reload()
491 	chregs->control = ctrl;  in dma_xec_reload()
506 	struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel);  in dma_xec_start()  local
508 	if (chregs->control & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS)) {  in dma_xec_start()
512 	chregs->ienable = 0u;  in dma_xec_start()
513 	chregs->istatus = 0xffu;  in dma_xec_start()
514 	chan_ctrl = chregs->control;  in dma_xec_start()
522 	chregs->ienable = BIT(XEC_DMA_CHAN_IES_BERR_POS) | BIT(XEC_DMA_CHAN_IES_DONE_POS);  in dma_xec_start()
523 	chregs->control = chan_ctrl;  in dma_xec_start()
524 	chregs->actv |= BIT(XEC_DMA_CHAN_ACTV_EN_POS);  in dma_xec_start()
539 	struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel);  in dma_xec_stop()  local
541 	chregs->ienable = 0;  in dma_xec_stop()
543 	if (chregs->control & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS)) {  in dma_xec_stop()
544 		chregs->ienable = 0;  in dma_xec_stop()
545 		chregs->control |= BIT(XEC_DMA_CHAN_CTRL_ABORT_POS);  in dma_xec_stop()
549 			if (!(chregs->control & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS))) {  in dma_xec_stop()
555 	chregs->mem_addr = chregs->mem_addr_end;  in dma_xec_stop()
556 	chregs->fsm = 0; /* delay */  in dma_xec_stop()
557 	chregs->control = 0;  in dma_xec_stop()
558 	chregs->istatus = 0xffu;  in dma_xec_stop()
559 	chregs->actv = 0;  in dma_xec_stop()
593 	struct dma_xec_chan_regs *chregs = xec_chan_regs(regs, channel);  in dma_xec_get_status()  local
595 	chan_ctrl = chregs->control;  in dma_xec_get_status()
601 						(chregs->mem_addr_end - chregs->mem_addr);  in dma_xec_get_status()