500 	uint32_t chan_ctrl = 0U;  in dma_xec_start()  local
514 	chan_ctrl = chregs->control;  in dma_xec_start()
516 	if (chan_ctrl & BIT(XEC_DMA_CHAN_CTRL_DIS_HWFL_POS)) {  in dma_xec_start()
517 		chan_ctrl |= BIT(XEC_DMA_CHAN_CTRL_SWFL_GO_POS);  in dma_xec_start()
519 		chan_ctrl |= BIT(XEC_DMA_CHAN_CTRL_HWFL_RUN_POS);  in dma_xec_start()
523 	chregs->control = chan_ctrl;  in dma_xec_start()
585 	uint32_t chan_ctrl = 0U;  in dma_xec_get_status()  local
595 	chan_ctrl = chregs->control;  in dma_xec_get_status()
597 	if (chan_ctrl & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS)) {  in dma_xec_get_status()
608 	if (chan_ctrl & BIT(XEC_DMA_CHAN_CTRL_DIS_HWFL_POS)) {  in dma_xec_get_status()
610 	} else if (chan_ctrl & BIT(XEC_DMA_CHAN_CTRL_M2D_POS)) {  in dma_xec_get_status()