Lines Matching +full:has +full:- +full:magic +full:- +full:addr

4  * SPDX-License-Identifier: Apache-2.0
10 /* Broadcom PAX-DMA RM register defines */
14 /* Per-Ring register offsets */
239  * AE_TIMEOUT is  (2^AE_TIMEOUT_BITS) - (2 * NumOfAEs * 2^FIFO_DEPTH_BITS)
241  * timeout val =  2^32 - 2*2*2^5
268 /* Register Per-ring RING_COMMON_CONTROL fields */
293  * set, completion write pointers has to be checked on each interrupt
332 #define PAX_DMA_RING_BD_ALIGN_CHECK(addr) \  argument
333 	(!((addr) & ((0x1 << RING_BD_ALIGN_ORDER) - 1)))
334 #define RING_CMPL_ALIGN_CHECK(addr) \  argument
335 	(!((addr) & ((0x1 << RING_CMPL_ALIGN_ORDER) - 1)))
355 #define PAX_DMA_NEXT_TBL_INDEX		(PAX_DMA_RM_RING_BD_COUNT - 1)
363 /* Host and Card address need 4-byte alignment */
367 	((_pd)->ring[_r].ring_base + (_write_ptr))
368 #define RM_COMM_REG(_pd, _write_ptr) ((_pd)->rm_comm_base + (_write_ptr))
369 #define PAX_DMA_REG(_pd, _write_ptr) ((_pd)->dma_base + (_write_ptr))
372 #define PAX_DMA_LAST_CMPL_IDX		(PAX_DMA_MAX_CMPL_COUNT - 1)
377 	((wptr) - (rptr)) : (PAX_DMA_MAX_CMPL_COUNT - (rptr) + (wptr)))
379 /* location of current cmpl pkt, take care of pointer wrap-around */
381 	(((wptr) == 0) ? PAX_DMA_LAST_CMPL_IDX : (wptr) - 1)
434 /* magic to sync completion of posted writes to host */
438 	/* ring-id 0-3 */
440 	/* opaque-id 0-31 */
442 	/* magic pattern */
463 	/* Per-Ring register base */
477 	/* per-ring lock */
505 	/* Per-Ring data */
513 	/* Per-Ring register base addr */