Lines Matching refs:dw_read
64 cap = dw_read(dev_cfg->shim, 0x0); in intel_adsp_gpdma_dump_registers()
65 ctl = dw_read(dev_cfg->shim, 0x4); in intel_adsp_gpdma_dump_registers()
66 ipptr = dw_read(dev_cfg->shim, 0x8); in intel_adsp_gpdma_dump_registers()
67 llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_dump_registers()
68 llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_dump_registers()
69 llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_dump_registers()
77 dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i])); in intel_adsp_gpdma_dump_registers()
84 dw_read(dw_cfg->base, ip_reg_offs[i])); in intel_adsp_gpdma_dump_registers()
107 val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_llp_enable()
122 val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_llp_disable()
136 tmp = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_llp_read()
137 *llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_llp_read()
138 *llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_llp_read()
141 *llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_llp_read()