18 #define GPDMA_CHLLPC_OFFSET(channel) (0x0010 + channel*0x10)  argument
23 #define GPDMA_CHLLPL(channel) (0x0018 + channel*0x10)  argument
24 #define GPDMA_CHLLPU(channel) (0x001c + channel*0x10)  argument
56 static void intel_adsp_gpdma_dump_registers(const struct device *dev, uint32_t channel)  in intel_adsp_gpdma_dump_registers()  argument
67 	llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_dump_registers()
68 	llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_dump_registers()
69 	llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_dump_registers()
72 		channel, cap, ctl, ipptr, llpc, llpl, llpu);  in intel_adsp_gpdma_dump_registers()
77 			dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i]));  in intel_adsp_gpdma_dump_registers()
90 					uint32_t channel, uint32_t dma_slot)  in intel_adsp_gpdma_llp_config()  argument
95 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_config()
101 					       uint32_t channel)  in intel_adsp_gpdma_llp_enable()  argument
107 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_enable()
109 		dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_enable()
116 						uint32_t channel)  in intel_adsp_gpdma_llp_disable()  argument
122 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_disable()
123 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_disable()
129 					uint32_t channel, uint32_t *llp_l,  in intel_adsp_gpdma_llp_read()  argument
136 	tmp = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
137 	*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
138 	*llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
141 		*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
147 static int intel_adsp_gpdma_config(const struct device *dev, uint32_t channel,  in intel_adsp_gpdma_config()  argument
150 	int res = dw_dma_config(dev, channel, cfg);  in intel_adsp_gpdma_config()
160 		LOG_DBG("%s: channel %d configuring llp for %x", dev->name, channel, cfg->dma_slot);  in intel_adsp_gpdma_config()
161 		intel_adsp_gpdma_llp_config(dev, channel, cfg->dma_slot);  in intel_adsp_gpdma_config()
170 static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel)  in intel_adsp_gpdma_start()  argument
192 	intel_adsp_gpdma_llp_enable(dev, channel);  in intel_adsp_gpdma_start()
193 	ret = dw_dma_start(dev, channel);  in intel_adsp_gpdma_start()
195 		intel_adsp_gpdma_llp_disable(dev, channel);  in intel_adsp_gpdma_start()
211 static int intel_adsp_gpdma_stop(const struct device *dev, uint32_t channel)  in intel_adsp_gpdma_stop()  argument
213 	int ret = dw_dma_stop(dev, channel);  in intel_adsp_gpdma_stop()
216 		intel_adsp_gpdma_llp_disable(dev, channel);  in intel_adsp_gpdma_stop()
222 static int intel_adsp_gpdma_copy(const struct device *dev, uint32_t channel,  in intel_adsp_gpdma_copy()  argument
228 	if (channel >= DW_MAX_CHAN) {  in intel_adsp_gpdma_copy()
232 	chan_data = &dev_data->chan[channel];  in intel_adsp_gpdma_copy()
397 int intel_adsp_gpdma_get_status(const struct device *dev, uint32_t channel, struct dma_status *stat)  in intel_adsp_gpdma_get_status()  argument
402 	if (channel >= DW_MAX_CHAN) {  in intel_adsp_gpdma_get_status()
406 	intel_adsp_gpdma_llp_read(dev, channel, &llp_l, &llp_u);  in intel_adsp_gpdma_get_status()
409 	return dw_dma_get_status(dev, channel, stat);  in intel_adsp_gpdma_get_status()