52 	uint32_t shim;  member
64 	cap = dw_read(dev_cfg->shim, 0x0);  in intel_adsp_gpdma_dump_registers()
65 	ctl = dw_read(dev_cfg->shim, 0x4);  in intel_adsp_gpdma_dump_registers()
66 	ipptr = dw_read(dev_cfg->shim, 0x8);  in intel_adsp_gpdma_dump_registers()
67 	llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_dump_registers()
68 	llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_dump_registers()
69 	llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_dump_registers()
95 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_config()
107 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_enable()
109 		dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_enable()
122 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_disable()
123 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_disable()
136 	tmp = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
137 	*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
138 	*llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
141 		*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
254 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_clock_enable()
271 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_clock_disable()
284 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_claim_ownership()
302 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_release_ownership()
318 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_enable()
334 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_disable()
535 		.shim = DT_INST_PROP_BY_IDX(inst, shim, 0),		\