4  * SPDX-License-Identifier: Apache-2.0
58 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_dump_registers()
59 	const struct dw_dma_dev_cfg *const dw_cfg = &dev_cfg->dw_cfg;  in intel_adsp_gpdma_dump_registers()
64 	cap = dw_read(dev_cfg->shim, 0x0);  in intel_adsp_gpdma_dump_registers()
65 	ctl = dw_read(dev_cfg->shim, 0x4);  in intel_adsp_gpdma_dump_registers()
66 	ipptr = dw_read(dev_cfg->shim, 0x8);  in intel_adsp_gpdma_dump_registers()
67 	llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_dump_registers()
68 	llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_dump_registers()
69 	llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_dump_registers()
71 	LOG_INF("%s: channel: %d cap %x, ctl %x, ipptr %x, llpc %x, llpl %x, llpu %x", dev->name,  in intel_adsp_gpdma_dump_registers()
76 		LOG_INF(" channel register offset: %#x value: %#x\n", chan_reg_offs[i],  in intel_adsp_gpdma_dump_registers()
77 			dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i]));  in intel_adsp_gpdma_dump_registers()
83 		LOG_INF(" ip register offset: %#x value: %#x\n", ip_reg_offs[i],  in intel_adsp_gpdma_dump_registers()
84 			dw_read(dw_cfg->base, ip_reg_offs[i]));  in intel_adsp_gpdma_dump_registers()
93 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_llp_config()
95 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_config()
104 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_llp_enable()
107 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_enable()
109 		dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_enable()
119 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_llp_disable()
122 	val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));  in intel_adsp_gpdma_llp_disable()
123 	dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),  in intel_adsp_gpdma_llp_disable()
133 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_llp_read()
136 	tmp = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
137 	*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
138 	*llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));  in intel_adsp_gpdma_llp_read()
140 		/* re-read the LLPU value, as LLPL just wrapped */  in intel_adsp_gpdma_llp_read()
141 		*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));  in intel_adsp_gpdma_llp_read()
157 	switch (cfg->channel_direction) {  in intel_adsp_gpdma_config()
160 		LOG_DBG("%s: channel %d configuring llp for %x", dev->name, channel, cfg->dma_slot);  in intel_adsp_gpdma_config()
161 		intel_adsp_gpdma_llp_config(dev, channel, cfg->dma_slot);  in intel_adsp_gpdma_config()
177 	/* We need to power-up device before using it. So in case of a GPDMA, we need to check if  in intel_adsp_gpdma_start()
181 	if (pm_device_state_get(dev, &state) != -ENOSYS) {  in intel_adsp_gpdma_start()
225 	struct dw_dma_dev_data *const dev_data = dev->data;  in intel_adsp_gpdma_copy()
229 		return -EINVAL;  in intel_adsp_gpdma_copy()
232 	chan_data = &dev_data->chan[channel];  in intel_adsp_gpdma_copy()
237 	for (int i = 0; i < chan_data->lli_count; i++) {  in intel_adsp_gpdma_copy()
238 		chan_data->lli[i].ctrl_hi &= ~DW_CTLH_DONE(1);  in intel_adsp_gpdma_copy()
241 	chan_data->ptr_data.current_ptr += size;  in intel_adsp_gpdma_copy()
242 	if (chan_data->ptr_data.current_ptr >= chan_data->ptr_data.end_ptr) {  in intel_adsp_gpdma_copy()
243 		chan_data->ptr_data.current_ptr = chan_data->ptr_data.start_ptr +  in intel_adsp_gpdma_copy()
244 			(chan_data->ptr_data.current_ptr - chan_data->ptr_data.end_ptr);  in intel_adsp_gpdma_copy()
250 /* Disables automatic clock gating (force disable clock gate) */
253 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_clock_enable()
254 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_clock_enable()
270 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_clock_disable()
271 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_clock_disable()
283 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_claim_ownership()
284 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_claim_ownership()
301 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_release_ownership()
302 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_release_ownership()
317 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_enable()
318 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_enable()
324 		return -1;  in intel_adsp_gpdma_enable()
333 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_disable()
334 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;  in intel_adsp_gpdma_disable()
344 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;  in intel_adsp_gpdma_power_on()
352 		LOG_ERR("%s: failed to initialize", dev->name);  in intel_adsp_gpdma_power_on()
360 	/* Disable dynamic clock gating appropriately before initializing */  in intel_adsp_gpdma_power_on()
366 		LOG_ERR("%s: failed to initialize", dev->name);  in intel_adsp_gpdma_power_on()
371 	dev_cfg->dw_cfg.irq_config();  in intel_adsp_gpdma_power_on()
373 	LOG_INF("%s: initialized", dev->name);  in intel_adsp_gpdma_power_on()
382 	LOG_INF("%s: power off", dev->name);  in intel_adsp_gpdma_power_off()
383 	/* Enabling dynamic clock gating */  in intel_adsp_gpdma_power_off()
403 		return -EINVAL;  in intel_adsp_gpdma_get_status()
407 	stat->total_copied = ((uint64_t)llp_u << 32) | llp_l;  in intel_adsp_gpdma_get_status()
428 		return -EINVAL;  in intel_adsp_gpdma_get_attribute()
460 		return -ENOTSUP;  in gpdma_pm_action()
468 	struct dw_dma_dev_data *const dev_data = dev->data;  in intel_adsp_gpdma_init()
471 	dev_data->dma_ctx.magic = DMA_MAGIC;  in intel_adsp_gpdma_init()
472 	dev_data->dma_ctx.dma_channels = DW_MAX_CHAN;  in intel_adsp_gpdma_init()
473 	dev_data->dma_ctx.atomic = dev_data->channels_atomic;  in intel_adsp_gpdma_init()