54 #define GD32_DMA_CHCTL(dma, ch)	  DMA_CHCTL((dma), (ch))  macro
97 	GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_PNAGA;  in gd32_dma_periph_increase_enable()
103 	GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_PNAGA;  in gd32_dma_periph_increase_disable()
109 	GD32_DMA_CHCTL(reg, ch) |= GD32_DMA_CHXCTL_M2M;  in gd32_dma_transfer_set_memory_to_memory()
110 	GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_DIR;  in gd32_dma_transfer_set_memory_to_memory()
116 	GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_M2M;  in gd32_dma_transfer_set_memory_to_periph()
117 	GD32_DMA_CHCTL(reg, ch) |= GD32_DMA_CHXCTL_DIR;  in gd32_dma_transfer_set_memory_to_periph()
123 	GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_M2M;  in gd32_dma_transfer_set_periph_to_memory()
124 	GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_DIR;  in gd32_dma_transfer_set_periph_to_memory()
130 	GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_MNAGA;  in gd32_dma_memory_increase_enable()
136 	GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_MNAGA;  in gd32_dma_memory_increase_disable()
142 	GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_CMEN;  in gd32_dma_circulation_enable()
148 	GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CMEN;  in gd32_dma_circulation_disable()
153 	GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_CHEN;  in gd32_dma_channel_enable()
158 	GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CHEN;  in gd32_dma_channel_disable()
164 	GD32_DMA_CHCTL(reg, ch) |= source;  in gd32_dma_interrupt_enable()
170 	GD32_DMA_CHCTL(reg, ch) &= ~source;  in gd32_dma_interrupt_disable()
176 	uint32_t ctl = GD32_DMA_CHCTL(reg, ch);  in gd32_dma_priority_config()
178 	GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_PRIO)) | priority;  in gd32_dma_priority_config()
184 	uint32_t ctl = GD32_DMA_CHCTL(reg, ch);  in gd32_dma_memory_width_config()
186 	GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_MWIDTH)) | mwidth;  in gd32_dma_memory_width_config()
192 	uint32_t ctl = GD32_DMA_CHCTL(reg, ch);  in gd32_dma_periph_width_config()
194 	GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_PWIDTH)) | pwidth;  in gd32_dma_periph_width_config()
202 	uint32_t ctl = GD32_DMA_CHCTL(reg, ch);  in gd32_dma_channel_subperipheral_select()
204 	GD32_DMA_CHCTL(reg, ch) =  in gd32_dma_channel_subperipheral_select()
282 	GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CHEN;  in gd32_dma_deinit()
284 	GD32_DMA_CHCTL(reg, ch) = DMA_CHCTL_RESET_VALUE;  in gd32_dma_deinit()