Lines Matching full:reg
62 uint32_t reg; member
95 gd32_dma_periph_increase_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_periph_increase_enable() argument
97 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_PNAGA; in gd32_dma_periph_increase_enable()
101 gd32_dma_periph_increase_disable(uint32_t reg, dma_channel_enum ch) in gd32_dma_periph_increase_disable() argument
103 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_PNAGA; in gd32_dma_periph_increase_disable()
107 gd32_dma_transfer_set_memory_to_memory(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_set_memory_to_memory() argument
109 GD32_DMA_CHCTL(reg, ch) |= GD32_DMA_CHXCTL_M2M; in gd32_dma_transfer_set_memory_to_memory()
110 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_DIR; in gd32_dma_transfer_set_memory_to_memory()
114 gd32_dma_transfer_set_memory_to_periph(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_set_memory_to_periph() argument
116 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_M2M; in gd32_dma_transfer_set_memory_to_periph()
117 GD32_DMA_CHCTL(reg, ch) |= GD32_DMA_CHXCTL_DIR; in gd32_dma_transfer_set_memory_to_periph()
121 gd32_dma_transfer_set_periph_to_memory(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_set_periph_to_memory() argument
123 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_M2M; in gd32_dma_transfer_set_periph_to_memory()
124 GD32_DMA_CHCTL(reg, ch) &= ~GD32_DMA_CHXCTL_DIR; in gd32_dma_transfer_set_periph_to_memory()
128 gd32_dma_memory_increase_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_memory_increase_enable() argument
130 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_MNAGA; in gd32_dma_memory_increase_enable()
134 gd32_dma_memory_increase_disable(uint32_t reg, dma_channel_enum ch) in gd32_dma_memory_increase_disable() argument
136 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_MNAGA; in gd32_dma_memory_increase_disable()
140 gd32_dma_circulation_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_circulation_enable() argument
142 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_CMEN; in gd32_dma_circulation_enable()
146 gd32_dma_circulation_disable(uint32_t reg, dma_channel_enum ch) in gd32_dma_circulation_disable() argument
148 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CMEN; in gd32_dma_circulation_disable()
151 static inline void gd32_dma_channel_enable(uint32_t reg, dma_channel_enum ch) in gd32_dma_channel_enable() argument
153 GD32_DMA_CHCTL(reg, ch) |= DMA_CHXCTL_CHEN; in gd32_dma_channel_enable()
156 static inline void gd32_dma_channel_disable(uint32_t reg, dma_channel_enum ch) in gd32_dma_channel_disable() argument
158 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CHEN; in gd32_dma_channel_disable()
162 gd32_dma_interrupt_enable(uint32_t reg, dma_channel_enum ch, uint32_t source) in gd32_dma_interrupt_enable() argument
164 GD32_DMA_CHCTL(reg, ch) |= source; in gd32_dma_interrupt_enable()
168 gd32_dma_interrupt_disable(uint32_t reg, dma_channel_enum ch, uint32_t source) in gd32_dma_interrupt_disable() argument
170 GD32_DMA_CHCTL(reg, ch) &= ~source; in gd32_dma_interrupt_disable()
174 gd32_dma_priority_config(uint32_t reg, dma_channel_enum ch, uint32_t priority) in gd32_dma_priority_config() argument
176 uint32_t ctl = GD32_DMA_CHCTL(reg, ch); in gd32_dma_priority_config()
178 GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_PRIO)) | priority; in gd32_dma_priority_config()
182 gd32_dma_memory_width_config(uint32_t reg, dma_channel_enum ch, uint32_t mwidth) in gd32_dma_memory_width_config() argument
184 uint32_t ctl = GD32_DMA_CHCTL(reg, ch); in gd32_dma_memory_width_config()
186 GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_MWIDTH)) | mwidth; in gd32_dma_memory_width_config()
190 gd32_dma_periph_width_config(uint32_t reg, dma_channel_enum ch, uint32_t pwidth) in gd32_dma_periph_width_config() argument
192 uint32_t ctl = GD32_DMA_CHCTL(reg, ch); in gd32_dma_periph_width_config()
194 GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_PWIDTH)) | pwidth; in gd32_dma_periph_width_config()
199 gd32_dma_channel_subperipheral_select(uint32_t reg, dma_channel_enum ch, in gd32_dma_channel_subperipheral_select() argument
202 uint32_t ctl = GD32_DMA_CHCTL(reg, ch); in gd32_dma_channel_subperipheral_select()
204 GD32_DMA_CHCTL(reg, ch) = in gd32_dma_channel_subperipheral_select()
211 gd32_dma_periph_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr) in gd32_dma_periph_address_config() argument
213 GD32_DMA_CHPADDR(reg, ch) = addr; in gd32_dma_periph_address_config()
217 gd32_dma_memory_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr) in gd32_dma_memory_address_config() argument
220 DMA_CHM0ADDR(reg, ch) = addr; in gd32_dma_memory_address_config()
222 GD32_DMA_CHMADDR(reg, ch) = addr; in gd32_dma_memory_address_config()
227 gd32_dma_transfer_number_config(uint32_t reg, dma_channel_enum ch, uint32_t num) in gd32_dma_transfer_number_config() argument
229 GD32_DMA_CHCNT(reg, ch) = (num & DMA_CHXCNT_CNT); in gd32_dma_transfer_number_config()
233 gd32_dma_transfer_number_get(uint32_t reg, dma_channel_enum ch) in gd32_dma_transfer_number_get() argument
235 return GD32_DMA_CHCNT(reg, ch); in gd32_dma_transfer_number_get()
239 gd32_dma_interrupt_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag) in gd32_dma_interrupt_flag_clear() argument
243 DMA_INTC0(reg) |= DMA_FLAG_ADD(flag, ch); in gd32_dma_interrupt_flag_clear()
245 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_interrupt_flag_clear()
248 GD32_DMA_INTC(reg) |= DMA_FLAG_ADD(flag, ch); in gd32_dma_interrupt_flag_clear()
253 gd32_dma_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag) in gd32_dma_flag_clear() argument
257 DMA_INTC0(reg) |= DMA_FLAG_ADD(flag, ch); in gd32_dma_flag_clear()
259 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_flag_clear()
262 GD32_DMA_INTC(reg) |= DMA_FLAG_ADD(flag, ch); in gd32_dma_flag_clear()
267 gd32_dma_interrupt_flag_get(uint32_t reg, dma_channel_enum ch, uint32_t flag) in gd32_dma_interrupt_flag_get() argument
271 return (DMA_INTF0(reg) & DMA_FLAG_ADD(flag, ch)); in gd32_dma_interrupt_flag_get()
273 return (DMA_INTF1(reg) & DMA_FLAG_ADD(flag, ch - DMA_CH4)); in gd32_dma_interrupt_flag_get()
276 return (GD32_DMA_INTF(reg) & DMA_FLAG_ADD(flag, ch)); in gd32_dma_interrupt_flag_get()
280 static inline void gd32_dma_deinit(uint32_t reg, dma_channel_enum ch) in gd32_dma_deinit() argument
282 GD32_DMA_CHCTL(reg, ch) &= ~DMA_CHXCTL_CHEN; in gd32_dma_deinit()
284 GD32_DMA_CHCTL(reg, ch) = DMA_CHCTL_RESET_VALUE; in gd32_dma_deinit()
285 GD32_DMA_CHCNT(reg, ch) = DMA_CHCNT_RESET_VALUE; in gd32_dma_deinit()
286 GD32_DMA_CHPADDR(reg, ch) = DMA_CHPADDR_RESET_VALUE; in gd32_dma_deinit()
288 DMA_CHM0ADDR(reg, ch) = DMA_CHMADDR_RESET_VALUE; in gd32_dma_deinit()
289 DMA_CHFCTL(reg, ch) = DMA_CHFCTL_RESET_VALUE; in gd32_dma_deinit()
291 DMA_INTC0(reg) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch); in gd32_dma_deinit()
293 DMA_INTC1(reg) |= in gd32_dma_deinit()
297 GD32_DMA_CHMADDR(reg, ch) = DMA_CHMADDR_RESET_VALUE; in gd32_dma_deinit()
298 GD32_DMA_INTC(reg) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch); in gd32_dma_deinit()
424 gd32_dma_deinit(cfg->reg, channel); in dma_gd32_config()
436 gd32_dma_transfer_set_memory_to_memory(cfg->reg, channel); in dma_gd32_config()
441 gd32_dma_transfer_set_periph_to_memory(cfg->reg, channel); in dma_gd32_config()
446 gd32_dma_transfer_set_memory_to_periph(cfg->reg, channel); in dma_gd32_config()
452 gd32_dma_memory_address_config(cfg->reg, channel, memory_cfg->addr); in dma_gd32_config()
454 gd32_dma_memory_increase_enable(cfg->reg, channel); in dma_gd32_config()
456 gd32_dma_memory_increase_disable(cfg->reg, channel); in dma_gd32_config()
459 gd32_dma_periph_address_config(cfg->reg, channel, periph_cfg->addr); in dma_gd32_config()
461 gd32_dma_periph_increase_enable(cfg->reg, channel); in dma_gd32_config()
463 gd32_dma_periph_increase_disable(cfg->reg, channel); in dma_gd32_config()
466 gd32_dma_transfer_number_config(cfg->reg, channel, in dma_gd32_config()
468 gd32_dma_priority_config(cfg->reg, channel, in dma_gd32_config()
470 gd32_dma_memory_width_config(cfg->reg, channel, in dma_gd32_config()
472 gd32_dma_periph_width_config(cfg->reg, channel, in dma_gd32_config()
474 gd32_dma_circulation_disable(cfg->reg, channel); in dma_gd32_config()
477 gd32_dma_channel_subperipheral_select(cfg->reg, channel, in dma_gd32_config()
505 gd32_dma_channel_disable(cfg->reg, ch); in dma_gd32_reload()
507 gd32_dma_transfer_number_config(cfg->reg, ch, size); in dma_gd32_reload()
512 gd32_dma_memory_address_config(cfg->reg, ch, dst); in dma_gd32_reload()
513 gd32_dma_periph_address_config(cfg->reg, ch, src); in dma_gd32_reload()
516 gd32_dma_memory_address_config(cfg->reg, ch, src); in dma_gd32_reload()
517 gd32_dma_periph_address_config(cfg->reg, ch, dst); in dma_gd32_reload()
521 gd32_dma_channel_enable(cfg->reg, ch); in dma_gd32_reload()
537 gd32_dma_interrupt_enable(cfg->reg, ch, in dma_gd32_start()
539 gd32_dma_channel_enable(cfg->reg, ch); in dma_gd32_start()
557 cfg->reg, ch, DMA_CHXCTL_FTFIE | GD32_DMA_INTERRUPT_ERRORS); in dma_gd32_stop()
558 gd32_dma_interrupt_flag_clear(cfg->reg, ch, in dma_gd32_stop()
560 gd32_dma_channel_disable(cfg->reg, ch); in dma_gd32_stop()
578 stat->pending_length = gd32_dma_transfer_number_get(cfg->reg, ch); in dma_gd32_get_status()
612 gd32_dma_interrupt_disable(cfg->reg, i, in dma_gd32_init()
614 gd32_dma_deinit(cfg->reg, i); in dma_gd32_init()
630 errflag = gd32_dma_interrupt_flag_get(cfg->reg, i, in dma_gd32_isr()
633 gd32_dma_interrupt_flag_get(cfg->reg, i, DMA_FLAG_FTF); in dma_gd32_isr()
644 cfg->reg, i, DMA_FLAG_FTF | GD32_DMA_FLAG_ERRORS); in dma_gd32_isr()
677 .reg = DT_INST_REG_ADDR(inst), \