46 #define DMA_CHCTL(dma, ch)   REG32((dma + 0x08UL) + 0x14UL * (uint32_t)(ch))  argument
47 #define DMA_CHCNT(dma, ch)   REG32((dma + 0x0CUL) + 0x14UL * (uint32_t)(ch))  argument
48 #define DMA_CHPADDR(dma, ch) REG32((dma + 0x10UL) + 0x14UL * (uint32_t)(ch))  argument
49 #define DMA_CHMADDR(dma, ch) REG32((dma + 0x14UL) + 0x14UL * (uint32_t)(ch))  argument
54 #define GD32_DMA_CHCTL(dma, ch)	  DMA_CHCTL((dma), (ch))  argument
55 #define GD32_DMA_CHCNT(dma, ch)	  DMA_CHCNT((dma), (ch))  argument
56 #define GD32_DMA_CHPADDR(dma, ch) DMA_CHPADDR((dma), (ch))  argument
57 #define GD32_DMA_CHMADDR(dma, ch) DMA_CHMADDR((dma), (ch))  argument
95 gd32_dma_periph_increase_enable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_periph_increase_enable()
101 gd32_dma_periph_increase_disable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_periph_increase_disable()
107 gd32_dma_transfer_set_memory_to_memory(uint32_t reg, dma_channel_enum ch)  in gd32_dma_transfer_set_memory_to_memory()
114 gd32_dma_transfer_set_memory_to_periph(uint32_t reg, dma_channel_enum ch)  in gd32_dma_transfer_set_memory_to_periph()
121 gd32_dma_transfer_set_periph_to_memory(uint32_t reg, dma_channel_enum ch)  in gd32_dma_transfer_set_periph_to_memory()
128 gd32_dma_memory_increase_enable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_memory_increase_enable()
134 gd32_dma_memory_increase_disable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_memory_increase_disable()
140 gd32_dma_circulation_enable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_circulation_enable()
146 gd32_dma_circulation_disable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_circulation_disable()
151 static inline void gd32_dma_channel_enable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_channel_enable()
156 static inline void gd32_dma_channel_disable(uint32_t reg, dma_channel_enum ch)  in gd32_dma_channel_disable()
162 gd32_dma_interrupt_enable(uint32_t reg, dma_channel_enum ch, uint32_t source)  in gd32_dma_interrupt_enable()
168 gd32_dma_interrupt_disable(uint32_t reg, dma_channel_enum ch, uint32_t source)  in gd32_dma_interrupt_disable()
174 gd32_dma_priority_config(uint32_t reg, dma_channel_enum ch, uint32_t priority)  in gd32_dma_priority_config()
182 gd32_dma_memory_width_config(uint32_t reg, dma_channel_enum ch, uint32_t mwidth)  in gd32_dma_memory_width_config()
190 gd32_dma_periph_width_config(uint32_t reg, dma_channel_enum ch, uint32_t pwidth)  in gd32_dma_periph_width_config()
199 gd32_dma_channel_subperipheral_select(uint32_t reg, dma_channel_enum ch,  in gd32_dma_channel_subperipheral_select()
211 gd32_dma_periph_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr)  in gd32_dma_periph_address_config()
217 gd32_dma_memory_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr)  in gd32_dma_memory_address_config()
227 gd32_dma_transfer_number_config(uint32_t reg, dma_channel_enum ch, uint32_t num)  in gd32_dma_transfer_number_config()
233 gd32_dma_transfer_number_get(uint32_t reg, dma_channel_enum ch)  in gd32_dma_transfer_number_get()
239 gd32_dma_interrupt_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)  in gd32_dma_interrupt_flag_clear()
253 gd32_dma_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)  in gd32_dma_flag_clear()
267 gd32_dma_interrupt_flag_get(uint32_t reg, dma_channel_enum ch, uint32_t flag)  in gd32_dma_interrupt_flag_get()
280 static inline void gd32_dma_deinit(uint32_t reg, dma_channel_enum ch)  in gd32_dma_deinit()
489 static int dma_gd32_reload(const struct device *dev, uint32_t ch, uint32_t src,  in dma_gd32_reload()
526 static int dma_gd32_start(const struct device *dev, uint32_t ch)  in dma_gd32_start()
545 static int dma_gd32_stop(const struct device *dev, uint32_t ch)  in dma_gd32_stop()
566 static int dma_gd32_get_status(const struct device *dev, uint32_t ch,  in dma_gd32_get_status()
585 static bool dma_gd32_api_chan_filter(const struct device *dev, int ch,  in dma_gd32_api_chan_filter()