59 	uint8_t channel_id;  member
86 	gdma_ll_rx_clear_interrupt_status(data->hal.dev, rx->channel_id, intr_status);  in dma_esp32_isr_handle_rx()
101 		rx->cb(dev, rx->user_data, rx->channel_id * 2, status);  in dma_esp32_isr_handle_rx()
110 	gdma_ll_tx_clear_interrupt_status(data->hal.dev, tx->channel_id, intr_status);  in dma_esp32_isr_handle_tx()
115 		tx->cb(dev, tx->user_data, tx->channel_id * 2 + 1, -intr_status);  in dma_esp32_isr_handle_tx()
128 	intr_status = gdma_ll_rx_get_interrupt_status(data->hal.dev, dma_channel_rx->channel_id);  in dma_esp32_isr_handle()
133 	intr_status = gdma_ll_tx_get_interrupt_status(data->hal.dev, dma_channel_tx->channel_id);  in dma_esp32_isr_handle()
194 	gdma_ll_rx_reset_channel(data->hal.dev, dma_channel->channel_id);  in dma_esp32_config_rx()
197 		data->hal.dev, dma_channel->channel_id,  in dma_esp32_config_rx()
207 		gdma_ll_rx_enable_data_burst(data->hal.dev, dma_channel->channel_id,  in dma_esp32_config_rx()
209 		gdma_ll_rx_enable_descriptor_burst(data->hal.dev, dma_channel->channel_id,  in dma_esp32_config_rx()
216 	gdma_ll_rx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id, UINT32_MAX);  in dma_esp32_config_rx()
217 	gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id, UINT32_MAX,  in dma_esp32_config_rx()
279 	gdma_ll_tx_reset_channel(data->hal.dev, dma_channel->channel_id);  in dma_esp32_config_tx()
282 		data->hal.dev, dma_channel->channel_id,  in dma_esp32_config_tx()
292 		gdma_ll_tx_enable_data_burst(data->hal.dev, dma_channel->channel_id, true);  in dma_esp32_config_tx()
293 		gdma_ll_tx_enable_descriptor_burst(data->hal.dev, dma_channel->channel_id, true);  in dma_esp32_config_tx()
299 	gdma_ll_tx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id, UINT32_MAX);  in dma_esp32_config_tx()
301 	gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id, GDMA_LL_EVENT_TX_EOF,  in dma_esp32_config_tx()
332 	dma_channel->channel_id = channel / 2;  in dma_esp32_config()
340 			&config->dma_channel[dma_channel->channel_id * 2];  in dma_esp32_config()
342 			&config->dma_channel[(dma_channel->channel_id * 2) + 1];  in dma_esp32_config()
344 		dma_channel_rx->channel_id = dma_channel->channel_id;  in dma_esp32_config()
345 		dma_channel_tx->channel_id = dma_channel->channel_id;  in dma_esp32_config()
380 			&config->dma_channel[dma_channel->channel_id * 2];  in dma_esp32_start()
382 			&config->dma_channel[(dma_channel->channel_id * 2) + 1];  in dma_esp32_start()
384 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
386 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
389 		gdma_ll_rx_set_desc_addr(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
391 		gdma_ll_rx_start(data->hal.dev, dma_channel->channel_id);  in dma_esp32_start()
393 		gdma_ll_tx_set_desc_addr(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
395 		gdma_ll_tx_start(data->hal.dev, dma_channel->channel_id);  in dma_esp32_start()
398 			gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
400 			gdma_ll_rx_set_desc_addr(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
402 			gdma_ll_rx_start(data->hal.dev, dma_channel->channel_id);  in dma_esp32_start()
404 			gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
406 			gdma_ll_tx_set_desc_addr(data->hal.dev, dma_channel->channel_id,  in dma_esp32_start()
408 			gdma_ll_tx_start(data->hal.dev, dma_channel->channel_id);  in dma_esp32_start()
430 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_stop()
432 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_stop()
434 		gdma_ll_rx_stop(data->hal.dev, dma_channel->channel_id);  in dma_esp32_stop()
435 		gdma_ll_tx_stop(data->hal.dev, dma_channel->channel_id);  in dma_esp32_stop()
439 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_stop()
441 		gdma_ll_rx_stop(data->hal.dev, dma_channel->channel_id);  in dma_esp32_stop()
443 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,  in dma_esp32_stop()
445 		gdma_ll_tx_stop(data->hal.dev, dma_channel->channel_id);  in dma_esp32_stop()
471 		status->busy = !gdma_ll_rx_is_fsm_idle(data->hal.dev, dma_channel->channel_id);  in dma_esp32_get_status()
474 			data->hal.dev, dma_channel->channel_id);  in dma_esp32_get_status()
482 		status->busy = !gdma_ll_tx_is_fsm_idle(data->hal.dev, dma_channel->channel_id);  in dma_esp32_get_status()
485 			data->hal.dev, dma_channel->channel_id);  in dma_esp32_get_status()
509 		gdma_ll_rx_reset_channel(data->hal.dev, dma_channel->channel_id);  in dma_esp32_reload()
512 		gdma_ll_tx_reset_channel(data->hal.dev, dma_channel->channel_id);  in dma_esp32_reload()