156 	uint64_t ctl;  member
372 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_8);  in dma_dw_axi_set_data_width()
376 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_16);  in dma_dw_axi_set_data_width()
380 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_32);  in dma_dw_axi_set_data_width()
384 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_64);  in dma_dw_axi_set_data_width()
388 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_128);  in dma_dw_axi_set_data_width()
392 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_256);  in dma_dw_axi_set_data_width()
396 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_WIDTH(BITS_512);  in dma_dw_axi_set_data_width()
406 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_8);  in dma_dw_axi_set_data_width()
410 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_16);  in dma_dw_axi_set_data_width()
414 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_32);  in dma_dw_axi_set_data_width()
418 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_64);  in dma_dw_axi_set_data_width()
422 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_128);  in dma_dw_axi_set_data_width()
426 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_256);  in dma_dw_axi_set_data_width()
430 		lli_desc->ctl |= DMA_DW_AXI_CTL_DST_WIDTH(BITS_512);  in dma_dw_axi_set_data_width()
530 		lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_STAT_EN |  in dma_dw_axi_config()
548 			lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |  in dma_dw_axi_config()
554 			lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |  in dma_dw_axi_config()
562 			lli_desc->ctl |= DMA_DW_AXI_CTL_SRC_MSIZE(msize_src) |  in dma_dw_axi_config()
585 		lli_desc->ctl |= DMA_DW_AXI_CTL_LLI_VALID;  in dma_dw_axi_config()
588 			lli_desc->ctl |= DMA_DW_AXI_CTL_LLI_LAST | DMA_DW_AXI_CTL_LLI_VALID;  in dma_dw_axi_config()
689 	sys_write64(lli_desc->ctl, reg_base + DMA_DW_AXI_CH_CTL(channel));  in dma_dw_axi_start()