288 	unsigned int channel;  in dma_dw_axi_isr()  local
297 	channel = find_lsb_set(status) - 1;  in dma_dw_axi_isr()
298 	if (channel < 0) {  in dma_dw_axi_isr()
299 		LOG_ERR("Spurious interrupt received channel:%u\n", channel);  in dma_dw_axi_isr()
303 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_isr()
304 		LOG_ERR("Interrupt received on invalid channel:%d\n", channel);  in dma_dw_axi_isr()
309 	chan_data = &dw_dev_data->chan[channel];  in dma_dw_axi_isr()
312 	ch_status = sys_read64(reg_base + DMA_DW_AXI_CH_INTSTATUS(channel));  in dma_dw_axi_isr()
321 			reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));  in dma_dw_axi_isr()
323 				channel, ch_status);  in dma_dw_axi_isr()
330 				reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));  in dma_dw_axi_isr()
334 				chan_data->priv_data_blk_tfr, channel, ret_status);  in dma_dw_axi_isr()
341 				reg_base + DMA_DW_AXI_CH_INTCLEARREG(channel));  in dma_dw_axi_isr()
345 						channel, ret_status);  in dma_dw_axi_isr()
346 			chan_data->ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_isr()
440 static int dma_dw_axi_config(const struct device *dev, uint32_t channel,  in dma_dw_axi_config()  argument
457 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_config()
458 		LOG_ERR("invalid dma channel %d", channel);  in dma_dw_axi_config()
463 	ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_config()
465 		LOG_ERR("DMA channel:%d is not idle(status:%d)", channel, ch_state);  in dma_dw_axi_config()
477 			" max descriptors in pool: %d", dev->name, channel,  in dma_dw_axi_config()
490 	chan_data = &dw_dev_data->chan[channel];  in dma_dw_axi_config()
494 		LOG_ERR("DMA channel:%d is busy", channel);  in dma_dw_axi_config()
508 			&dw_dev_data->dma_desc_pool[channel * CONFIG_DMA_DW_AXI_MAX_DESC];  in dma_dw_axi_config()
572 				__func__, dev->name, channel, cfg->channel_direction);  in dma_dw_axi_config()
637 static int dma_dw_axi_start(const struct device *dev, uint32_t channel)  in dma_dw_axi_start()  argument
646 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_start()
647 		LOG_ERR("invalid dma channel %d", channel);  in dma_dw_axi_start()
652 	ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_start()
654 		LOG_ERR("DMA channel:%d is not idle", channel);  in dma_dw_axi_start()
659 	chan_data = &dw_dev_data->chan[channel];  in dma_dw_axi_start()
669 	sys_write64(chan_data->cfg, reg_base + DMA_DW_AXI_CH_CFG(channel));  in dma_dw_axi_start()
672 				reg_base + DMA_DW_AXI_CH_INTSTATUS_ENABLEREG(channel));  in dma_dw_axi_start()
674 				reg_base + DMA_DW_AXI_CH_INTSIGNAL_ENABLEREG(channel));  in dma_dw_axi_start()
679 	sys_write64(((uint64_t)lli_desc), reg_base + DMA_DW_AXI_CH_LLP(channel));  in dma_dw_axi_start()
682 	sys_write64(lli_desc->sar, reg_base + DMA_DW_AXI_CH_SAR(channel));  in dma_dw_axi_start()
683 	sys_write64(lli_desc->dar, reg_base + DMA_DW_AXI_CH_DAR(channel));  in dma_dw_axi_start()
686 			reg_base + DMA_DW_AXI_CH_BLOCK_TS(channel));  in dma_dw_axi_start()
689 	sys_write64(lli_desc->ctl, reg_base + DMA_DW_AXI_CH_CTL(channel));  in dma_dw_axi_start()
693 	sys_write64(CH_EN(channel), reg_base + DMA_DW_AXI_CHENREG);  in dma_dw_axi_start()
695 	chan_data->ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_start()
700 static int dma_dw_axi_stop(const struct device *dev, uint32_t channel)  in dma_dw_axi_stop()  argument
708 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_stop()
709 		LOG_ERR("invalid dma channel %d", channel);  in dma_dw_axi_stop()
714 	ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_stop()
728 	sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG);  in dma_dw_axi_stop()
731 	sys_clear_bit(reg_base + DMA_DW_AXI_CHENREG, channel);  in dma_dw_axi_stop()
733 	is_channel_busy = WAIT_FOR((sys_read64(reg_base + DMA_DW_AXI_CHENREG)) & (BIT(channel)),  in dma_dw_axi_stop()
737 		sys_write64(CH_ABORT(channel), reg_base + DMA_DW_AXI_CHENREG);  in dma_dw_axi_stop()
740 				(BIT(channel)), CONFIG_DMA_CHANNEL_STATUS_TIMEOUT,  in dma_dw_axi_stop()
751 static int dma_dw_axi_resume(const struct device *dev, uint32_t channel)  in dma_dw_axi_resume()  argument
759 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_resume()
760 		LOG_ERR("invalid dma channel %d", channel);  in dma_dw_axi_resume()
764 	ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_resume()
766 		LOG_INF("channel %u is not in suspended state so cannot resume channel", channel);  in dma_dw_axi_resume()
772 	WRITE_BIT(reg, CH_RESUME_WE(channel), 1);  in dma_dw_axi_resume()
774 	WRITE_BIT(reg, CH_RESUME(channel), 0);  in dma_dw_axi_resume()
782 static int dma_dw_axi_suspend(const struct device *dev, uint32_t channel)  in dma_dw_axi_suspend()  argument
790 	if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) {  in dma_dw_axi_suspend()
791 		LOG_ERR("invalid dma channel %u", channel);  in dma_dw_axi_suspend()
795 	ch_state = dma_dw_axi_get_ch_status(dev, channel);  in dma_dw_axi_suspend()
797 		LOG_INF("nothing to suspend as dma channel %u is not busy", channel);  in dma_dw_axi_suspend()
802 	sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG);  in dma_dw_axi_suspend()
804 	ret = WAIT_FOR(dma_dw_axi_get_ch_status(dev, channel) &  in dma_dw_axi_suspend()