Lines Matching refs:DMA_DW_AXI_CHENREG
35 #define DMA_DW_AXI_CHENREG 0x18 macro
268 ch_status = sys_read64(reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_get_ch_status()
693 sys_write64(CH_EN(channel), reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_start()
728 sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_stop()
731 sys_clear_bit(reg_base + DMA_DW_AXI_CHENREG, channel); in dma_dw_axi_stop()
733 is_channel_busy = WAIT_FOR((sys_read64(reg_base + DMA_DW_AXI_CHENREG)) & (BIT(channel)), in dma_dw_axi_stop()
737 sys_write64(CH_ABORT(channel), reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_stop()
739 is_channel_busy = WAIT_FOR((sys_read64(reg_base + DMA_DW_AXI_CHENREG)) & in dma_dw_axi_stop()
770 reg = sys_read64(reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_resume()
776 sys_write64(reg, reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_resume()
802 sys_write64(CH_SUSP(channel), reg_base + DMA_DW_AXI_CHENREG); in dma_dw_axi_suspend()