Lines Matching +full:chain +full:- +full:transfer
4 * SPDX-License-Identifier: Apache-2.0
23 #define DMA_ABORT(dev) (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x24)
25 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x30)
29 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x40 + DMA_CH_OFFSET(ch))
31 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x44 + DMA_CH_OFFSET(ch))
33 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x48 + DMA_CH_OFFSET(ch))
35 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x4C + DMA_CH_OFFSET(ch))
37 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x50 + DMA_CH_OFFSET(ch))
39 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x54 + DMA_CH_OFFSET(ch))
41 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x58 + DMA_CH_OFFSET(ch))
43 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x5C + DMA_CH_OFFSET(ch))
58 /* Source/Destination transfer width options */
152 struct dma_atcdmac300_data *const data = dev->data; in dma_atcdmac300_isr()
156 key = k_spin_lock(&data->lock); in dma_atcdmac300_isr()
161 k_spin_unlock(&data->lock, key); in dma_atcdmac300_isr()
166 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
169 ch_data = &data->chan[channel]; in dma_atcdmac300_isr()
170 if (ch_data->blkcallback) { in dma_atcdmac300_isr()
171 ch_data->blkcallback(dev, ch_data->blkuser_data, channel, 0); in dma_atcdmac300_isr()
173 data->chan[channel].status.busy = false; in dma_atcdmac300_isr()
179 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
182 ch_data = &data->chan[channel]; in dma_atcdmac300_isr()
183 if (ch_data->blkcallback) { in dma_atcdmac300_isr()
184 ch_data->blkcallback(dev, ch_data->blkuser_data, channel, -EIO); in dma_atcdmac300_isr()
192 struct dma_atcdmac300_data *const data = dev->data; in dma_atcdmac300_config()
199 return -EINVAL; in dma_atcdmac300_config()
202 __ASSERT_NO_MSG(cfg->source_data_size == cfg->dest_data_size); in dma_atcdmac300_config()
203 __ASSERT_NO_MSG(cfg->source_burst_length == cfg->dest_burst_length); in dma_atcdmac300_config()
205 if (cfg->source_data_size != 1 && cfg->source_data_size != 2 && in dma_atcdmac300_config()
206 cfg->source_data_size != 4) { in dma_atcdmac300_config()
208 ret = -EINVAL; in dma_atcdmac300_config()
212 cfg_blocks = cfg->head_block; in dma_atcdmac300_config()
214 ret = -EINVAL; in dma_atcdmac300_config()
218 tfr_size = cfg_blocks->block_size/cfg->source_data_size; in dma_atcdmac300_config()
220 ret = -EINVAL; in dma_atcdmac300_config()
226 switch (cfg->channel_direction) { in dma_atcdmac300_config()
230 ch_ctrl |= DMA_CH_CTRL_DSTREQ(cfg->dma_slot); in dma_atcdmac300_config()
234 ch_ctrl |= DMA_CH_CTRL_SRCREQ(cfg->dma_slot); in dma_atcdmac300_config()
238 ret = -EINVAL; in dma_atcdmac300_config()
243 switch (cfg_blocks->source_addr_adj) { in dma_atcdmac300_config()
254 ret = -EINVAL; in dma_atcdmac300_config()
258 switch (cfg_blocks->dest_addr_adj) { in dma_atcdmac300_config()
269 ret = -EINVAL; in dma_atcdmac300_config()
276 if (!cfg->error_callback_dis) { in dma_atcdmac300_config()
280 src_width = find_msb_set(cfg->source_data_size) - 1; in dma_atcdmac300_config()
281 dst_width = find_msb_set(cfg->dest_data_size) - 1; in dma_atcdmac300_config()
282 src_burst_size = find_msb_set(cfg->source_burst_length) - 1; in dma_atcdmac300_config()
292 key = k_spin_lock(&data->lock); in dma_atcdmac300_config()
295 k_spin_unlock(&data->lock, key); in dma_atcdmac300_config()
297 /* Set transfer size */ in dma_atcdmac300_config()
301 data->chan[channel].status.dir = cfg->channel_direction; in dma_atcdmac300_config()
302 data->chan[channel].status.pending_length = cfg->source_data_size; in dma_atcdmac300_config()
308 data->chan[channel].blkcallback = cfg->dma_callback; in dma_atcdmac300_config()
309 data->chan[channel].blkuser_data = cfg->user_data; in dma_atcdmac300_config()
314 sys_write32(cfg_blocks->source_address, in dma_atcdmac300_config()
317 sys_write32(cfg_blocks->dest_address, in dma_atcdmac300_config()
321 if (cfg->dest_chaining_en == 1 && cfg_blocks->next_block) { in dma_atcdmac300_config()
328 for (cfg_blocks = cfg_blocks->next_block; cfg_blocks != NULL; in dma_atcdmac300_config()
329 cfg_blocks = cfg_blocks->next_block) { in dma_atcdmac300_config()
334 switch (cfg_blocks->source_addr_adj) { in dma_atcdmac300_config()
345 ret = -EINVAL; in dma_atcdmac300_config()
349 switch (cfg_blocks->dest_addr_adj) { in dma_atcdmac300_config()
360 ret = -EINVAL; in dma_atcdmac300_config()
365 cfg_blocks->block_size/cfg->source_data_size; in dma_atcdmac300_config()
368 (uint32_t)cfg_blocks->source_address; in dma_atcdmac300_config()
372 (uint32_t)((long)cfg_blocks->dest_address); in dma_atcdmac300_config()
375 if (cfg_blocks->next_block) { in dma_atcdmac300_config()
389 /* Single transfer is supported, but Chain transfer is still in dma_atcdmac300_config()
406 return -EINVAL; in dma_atcdmac300_reload()
418 /* Set transfer size */ in dma_atcdmac300_reload()
427 struct dma_atcdmac300_data *const data = dev->data; in dma_atcdmac300_transfer_start()
430 return -EINVAL; in dma_atcdmac300_transfer_start()
436 data->chan[channel].status.busy = true; in dma_atcdmac300_transfer_start()
444 struct dma_atcdmac300_data *const data = dev->data; in dma_atcdmac300_transfer_stop()
448 return -EINVAL; in dma_atcdmac300_transfer_stop()
451 key = k_spin_lock(&data->lock); in dma_atcdmac300_transfer_stop()
456 data->chan[channel].status.busy = false; in dma_atcdmac300_transfer_stop()
458 k_spin_unlock(&data->lock, key); in dma_atcdmac300_transfer_stop()
465 const struct dma_atcdmac300_cfg *const config = (struct dma_atcdmac300_cfg *)dev->config; in dma_atcdmac300_init()
476 config->irq_config(); in dma_atcdmac300_init()
478 irq_enable(config->irq_num); in dma_atcdmac300_init()
487 struct dma_atcdmac300_data *const data = dev->data; in dma_atcdmac300_get_status()
489 stat->busy = data->chan[channel].status.busy; in dma_atcdmac300_get_status()
490 stat->dir = data->chan[channel].status.dir; in dma_atcdmac300_get_status()
491 stat->pending_length = data->chan[channel].status.pending_length; in dma_atcdmac300_get_status()