27 #define NT35510_COLMOD_RGB565 0x55
28 #define NT35510_COLMOD_RGB888 0x77
78 	{.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x01}},
80 	{.reg = 0xb0, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}},
82 	{.reg = 0xb6, .cmd_len = 3, .cmd = {0x46, 0x46, 0x46}},
84 	{.reg = 0xb1, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}},
86 	{.reg = 0xb7, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}},
88 	{.reg = 0xb2, .cmd_len = 3, .cmd = {0x00, 0x00, 0x02}},
90 	{.reg = 0xb8, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}},
92 	{.reg = 0xbf, .cmd_len = 1, .cmd = {0x01}},
94 	{.reg = 0xb3, .cmd_len = 3, .cmd = {0x09, 0x09, 0x09}},
96 	{.reg = 0xb9, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}},
98 	{.reg = 0xb5, .cmd_len = 3, .cmd = {0x08, 0x08, 0x08}},
100 	{.reg = 0xba, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}},
101 	/* VGMP/VGSP: 4.5V/0V */
102 	{.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}},
103 	/* VGMN/VGSN:-4.5V/0V */
104 	{.reg = 0xbd, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}},
106 	{.reg = 0xbe, .cmd_len = 2, .cmd = {0x00, 0x50}},
108 	/* LV2: Page 0 enable */
109 	{.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x00}},
111 	{.reg = 0xb1, .cmd_len = 2, .cmd = {0xfc, 0x00}},
113 	{.reg = 0xb6, .cmd_len = 1, .cmd = {0x03}},
115 	{.reg = 0xb5, .cmd_len = 1, .cmd = {0x51}},
117 	{.reg = 0xb7, .cmd_len = 2, .cmd = {0x00, 0x00}},
119 	{.reg = 0xb8, .cmd_len = 4, .cmd = {0x01, 0x02, 0x02, 0x02}},
121 	{.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x00, 0x00}},
123 	{.reg = 0xcc, .cmd_len = 3, .cmd = {0x03, 0x00, 0x00}},
125 	{.reg = 0xba, .cmd_len = 1, .cmd = {0x01}}};
128 	{.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x00}},
129 	{.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}},
130 	{.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}}};
133 	{.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x60}},
134 	{.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}},
135 	{.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}}};
139 	{.reg = NT35510_CMD_WRDISBV, .cmd_len = 1, .cmd = {0x7f}},
141 	{.reg = NT35510_CMD_WRCTRLD, .cmd_len = 1, .cmd = {0x2c}},
143 	{.reg = NT35510_CMD_WRCABC, .cmd_len = 1, .cmd = {0x02}},
145 	{.reg = NT35510_CMD_WRCABCMB, .cmd_len = 1, .cmd = {0xff}},
147 	{.reg = MIPI_DCS_SET_DISPLAY_ON, .cmd_len = 0, .cmd = {}},
152 	{.reg = NT35510_CMD_RAMWR, .cmd_len = 0, .cmd = {}},
162 	if (ret < 0) {  in nt35510_write_reg()
163 		LOG_ERR("Failed writing reg: 0x%x result: (%d)", reg, ret);  in nt35510_write_reg()
166 	return 0;  in nt35510_write_reg()
179 	int ret = 0;  in nt35510_write_sequence()
182 	for (int i = 0; i < nr_cmds && ret == 0; i++) {  in nt35510_write_sequence()
196 	if (ret < 0) {  in nt35510_config()
208 	if (ret < 0) {  in nt35510_config()
212 	ret = nt35510_write_reg(dev, NT35510_CMD_SLPOUT, NULL, 0);  in nt35510_config()
213 	if (ret < 0) {  in nt35510_config()
225 	if (ret < 0) {  in nt35510_config()
240 		ret = gpio_pin_set_dt(&cfg->backlight, 0);  in nt35510_blanking_on()
246 	return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);  in nt35510_blanking_on()
261 	return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);  in nt35510_blanking_off()
275 	memset(capabilities, 0, sizeof(struct display_capabilities));  in nt35510_get_capabilities()
290 		return 0;  in nt35510_set_pixel_format()
299 	uint8_t id = 0;  in nt35510_check_id()
309 		LOG_ERR("ID 0x%x, expected: 0x%x)", id, NT35510_ID);  in nt35510_check_id()
312 	return 0;  in nt35510_check_id()
328 		if (ret < 0) {  in nt35510_init()
334 		if (ret < 0) {  in nt35510_init()
342 	if (cfg->rotation == 0) {  in nt35510_init()
380 	if (ret < 0) {  in nt35510_init()
392 	if (ret < 0) {  in nt35510_init()
410 	return 0;  in nt35510_init()
424 		.reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),                            \
425 		.backlight = GPIO_DT_SPEC_INST_GET_OR(n, bl_gpios, {0}),                           \
426 		.data_lanes = DT_INST_PROP_BY_IDX(n, data_lanes, 0),                               \