29 #define HX8394_SETMIPI 0xBA
32 #define HX8394_MIPI_TA_6TL 0x3
33 #define HX8394_MIPI_DPHYCMD_LPRX_8NS 0x40
34 #define HX8394_MIPI_DPHYCMD_LPRX_66mV 0x20
35 #define HX8394_MIPI_DPHYCMD_LPTX_SRLIM 0x8
36 #define HX8394_MIPI_DPHYCMD_LDO_1_55V 0x60
37 #define HX8394_MIPI_DPHYCMD_HSRX_7X 0x8
38 #define HX8394_MIPI_DPHYCMD_HSRX_100OHM 0x2
39 #define HX8394_MIPI_DPHYCMD_LPCD_1X 0x1
41 #define HX8394_SET_ADDRESS 0x36
43 #define HX8394_FLIP_VERTICAL BIT(0)
45 #define HX8394_SETPOWER 0xB1
46 #define HX8394_POWER_AP_1_0UA 0x8
47 #define HX8394_POWER_HX5186 0x40
48 #define HX8394_POWER_VRHP_4_8V 0x12
49 #define HX8394_POWER_VRHN_4_8V 0x12
50 #define HX8394_POWER_VPPS_8_25V 0x60
51 #define HX8394_POWER_XDK_X2 0x1
52 #define HX8394_POWER_VSP_FBOFF 0x8
53 #define HX8394_POWER_FS0_DIV_8 0x2
54 #define HX8394_POWER_CLK_OPT_VGH_HSYNC_RST 0x10
55 #define HX8394_POWER_CLK_OPT_VGL_HSYNC_RST 0x20
56 #define HX8394_POWER_FS2_DIV_192 0x4
57 #define HX8394_POWER_FS1_DIV_224 0x50
58 #define HX8394_POWER_BTP_5_55V 0x11
59 #define HX8394_POWER_VGH_RATIO_2VSPVSN 0x60
60 #define HX8394_POWER_BTN_5_55V 0x11
61 #define HX8394_POWER_VGL_RATIO_2VSPVSN 0x60
62 #define HX8394_POWER_VGHS_16V 0x57
63 #define HX8394_POWER_VGLS_12_4V 0x47
65 #define HX8394_SETDISP 0xB2
66 #define HX8394_DISP_COL_INV 0x0
67 #define HX8394_DISP_MESSI_ENB 0x80
68 #define HX8394_DISP_NL_1280 0x64
69 #define HX8394_DISP_BP_14 0xC
70 #define HX8394_DISP_FP_15 0xD
71 #define HX8394_DISP_RTN_144 0x2F
73 #define HX8394_SETCYC 0xB4
75 #define HX8394_SETGIP0 0xD3
76 #define HX8394_GIP0_EQ_OPT_BOTH 0x0
77 #define HX8394_GIP0_EQ_HSYNC_NORMAL 0x0
78 #define HX8394_GIP0_EQ_VSEL_VSSA 0x0
79 #define HX8394_SHP_START_4 0x40
80 #define HX8394_SCP_WIDTH_7X_HSYNC 0x7
81 #define HX8394_CHR0_12X_HSYNC 0xA
82 #define HX8394_CHR1_18X_HSYNC 0x10
84 #define HX8394_SETGIP1 0xD5
86 #define HX8394_SETGIP2 0xD6
88 #define HX8394_SETVCOM 0xB6
89 #define HX8394_VCMC_F_1_76V 0x92
90 #define HX8394_VCMC_B_1_76V 0x92
92 #define HX8394_SETGAMMA 0xE0
94 #define HX8394_SETPANEL 0xCC
95 #define HX8394_COLOR_BGR BIT(0)
98 #define HX8394_SETBANK 0xBD
100 #define HX8394_SET_TEAR 0x35
101 #define HX8394_TEAR_VBLANK 0x0
103 #define HX8394_SETEXTC 0xB9
104 #define HX8394_EXTC1_MAGIC 0xFF
105 #define HX8394_EXTC2_MAGIC 0x83
106 #define HX8394_EXTC3_MAGIC 0x94
149 	0x73, /* SPON delay */
150 	0x74, /* SPOFF delay */
151 	0x73, /* CON delay */
152 	0x74, /* COFF delay */
153 	0x73, /* CON1 delay */
154 	0x74, /* COFF1 delay */
155 	0x1, /* EQON time */
156 	0xC, /* SON time */
157 	0x86, /* SOFF time */
158 	0x75, /* SAP1_P, SAP2 (1st and second stage op amp bias) */
159 	0x00, /* DX2 off, EQ off, EQ_MI off */
160 	0x3F, /* DX2 off period setting */
161 	0x73, /* SPON_MPU delay */
162 	0x74, /* SPOFF_MPU delay */
163 	0x73, /* CON_MPU delay */
164 	0x74, /* COFF_MPU delay */
165 	0x73, /* CON1_MPU delay */
166 	0x74, /* COFF1_MPU delay */
167 	0x1, /* EQON_MPU time */
168 	0xC, /* SON_MPU time */
169 	0x86 /* SOFF_MPU time */
176 	0x7, /* EQ_DELAY_ON1 (in cycles of TCON CLK */
177 	0x7, /* EQ_DELAY_OFF1 (in cycles of TCON CLK */
178 	0x40, /* GPWR signal frequency (64x per frame) */
179 	0x7, /* GPWR signal non overlap timing (in cycles of TCON */
180 	0xC, /* GIP dummy clock for first CKV */
181 	0x00, /* GIP dummy clock for second CKV */
185 	0x8, /* SHR0_2 = 8, SHR0_3 = 0 */
186 	0x10, /* SHR0_1 = 1, SHR0[11:8] = 0x0 */
187 	0x8, /* SHR0 = 0x8 */
188 	0x0, /* SHR0_GS[11:8]. Unset. */
189 	0x8, /* SHR0_GS = 0x8 */
190 	0x54, /* SHR1_3 = 0x5, SHR1_2 = 0x4 */
191 	0x15, /* SHR1_1 = 0x1, SHR1[11:8] = 0x5 */
192 	0xA, /* SHR1[7:0] = 0xA (SHR1 = 0x50A) */
193 	0x5, /* SHR1_GS[11:8] = 0x5 */
194 	0xA, /* SHR1_GS[7:0] = 0xA (SHR1_GS = 0x50A) */
195 	0x2, /* SHR2_3 = 0x0, SHR2_2 = 0x2 */
196 	0x15, /* SHR2_1 = 0x1, SHR2[11:8] = 0x5 */
197 	0x6, /* SHR2[7:0] = 0x6 (SHR2 = 0x506) */
198 	0x5, /* SHR2_GS[11:8] = 0x5 */
199 	0x6, /* SHR2_GS[7:0 = 0x6 (SHR2_GS = 0x506) */
201 	0x44, /* SHP2 = 0x4, SHP1 = 0x4 */
204 	0x4B, /* CHP0 = 4x hsync, CCP0 = 0xB */
206 	0x7, /* CHR1_GS = 9x hsync */
207 	0x7, /* CHP1 = 1x hsync, CCP1 = 0x7 */
209 	0xC,
210 	0x40
218 	0x1C, /* COS1_L */
219 	0x1C, /* COS1_R */
220 	0x1D, /* COS2_L */
221 	0x1D, /* COS2_R */
222 	0x00, /* COS3_L */
223 	0x01, /* COS3_R */
224 	0x02, /* COS4_L */
225 	0x03, /* COS4_R */
226 	0x04, /* COS5_L */
227 	0x05, /* COS5_R */
228 	0x06, /* COS6_L */
229 	0x07, /* COS6_R */
230 	0x08, /* COS7_L */
231 	0x09, /* COS7_R */
232 	0x0A, /* COS8_L */
233 	0x0B, /* COS8_R */
234 	0x24, /* COS9_L */
235 	0x25, /* COS9_R */
236 	0x18, /* COS10_L */
237 	0x18, /* COS10_R */
238 	0x26, /* COS11_L */
239 	0x27, /* COS11_R */
240 	0x18, /* COS12_L */
241 	0x18, /* COS12_R */
242 	0x18, /* COS13_L */
243 	0x18, /* COS13_R */
244 	0x18, /* COS14_L */
245 	0x18, /* COS14_R */
246 	0x18, /* COS15_L */
247 	0x18, /* COS15_R */
248 	0x18, /* COS16_L */
249 	0x18, /* COS16_R */
250 	0x18, /* COS17_L */
251 	0x18, /* COS17_R */
252 	0x18, /* COS18_L */
253 	0x18, /* COS18_R */
254 	0x18, /* COS19_L */
255 	0x18, /* COS19_R */
256 	0x20, /* COS20_L */
257 	0x21, /* COS20_R */
258 	0x18, /* COS21_L */
259 	0x18, /* COS21_R */
260 	0x18, /* COS22_L */
261 	0x18 /* COS22_R */
269 	0x1C, /* COS1_L_GS */
270 	0x1C, /* COS1_R_GS */
271 	0x1D, /* COS2_L_GS */
272 	0x1D, /* COS2_R_GS */
273 	0x07, /* COS3_L_GS */
274 	0x06, /* COS3_R_GS */
275 	0x05, /* COS4_L_GS */
276 	0x04, /* COS4_R_GS */
277 	0x03, /* COS5_L_GS */
278 	0x02, /* COS5_R_GS */
279 	0x01, /* COS6_L_GS */
280 	0x00, /* COS6_R_GS */
281 	0x0B, /* COS7_L_GS */
282 	0x0A, /* COS7_R_GS */
283 	0x09, /* COS8_L_GS */
284 	0x08, /* COS8_R_GS */
285 	0x21, /* COS9_L_GS */
286 	0x20, /* COS9_R_GS */
287 	0x18, /* COS10_L_GS */
288 	0x18, /* COS10_R_GS */
289 	0x27, /* COS11_L_GS */
290 	0x26, /* COS11_R_GS */
291 	0x18, /* COS12_L_GS */
292 	0x18, /* COS12_R_GS */
293 	0x18, /* COS13_L_GS */
294 	0x18, /* COS13_R_GS */
295 	0x18, /* COS14_L_GS */
296 	0x18, /* COS14_R_GS */
297 	0x18, /* COS15_L_GS */
298 	0x18, /* COS15_R_GS */
299 	0x18, /* COS16_L_GS */
300 	0x18, /* COS16_R_GS */
301 	0x18, /* COS17_L_GS */
302 	0x18, /* COS17_R_GS */
303 	0x18, /* COS18_L_GS */
304 	0x18, /* COS18_R_GS */
305 	0x18, /* COS19_L_GS */
306 	0x18, /* COS19_R_GS */
307 	0x25, /* COS20_L_GS */
308 	0x24, /* COS20_R_GS */
309 	0x18, /* COS21_L_GS */
310 	0x18, /* COS21_R_GS */
311 	0x18, /* COS22_L_GS */
312 	0x18  /* COS22_R_GS */
323 	0x00, /* VHP0 */
324 	0x0A, /* VHP1 */
325 	0x15, /* VHP2 */
326 	0x1B, /* VHP3 */
327 	0x1E, /* VHP4 */
328 	0x21, /* VHP5 */
329 	0x24, /* VHP6 */
330 	0x22, /* VHP7 */
331 	0x47, /* VMP0 */
332 	0x56, /* VMP1 */
333 	0x65, /* VMP2 */
334 	0x66, /* VMP3 */
335 	0x6E, /* VMP4 */
336 	0x82, /* VMP5 */
337 	0x88, /* VMP6 */
338 	0x8B, /* VMP7 */
339 	0x9A, /* VMP8 */
340 	0x9D, /* VMP9 */
341 	0x98, /* VMP10 */
342 	0xA8, /* VMP11 */
343 	0xB9, /* VMP12 */
344 	0x5D, /* VLP0 */
345 	0x5C, /* VLP1 */
346 	0x61, /* VLP2 */
347 	0x66, /* VLP3 */
348 	0x6A, /* VLP4 */
349 	0x6F, /* VLP5 */
350 	0x7F, /* VLP6 */
351 	0x7F, /* VLP7 */
352 	0x00, /* VHN0 */
353 	0x0A, /* VHN1 */
354 	0x15, /* VHN2 */
355 	0x1B, /* VHN3 */
356 	0x1E, /* VHN4 */
357 	0x21, /* VHN5 */
358 	0x24, /* VHN6 */
359 	0x22, /* VHN7 */
360 	0x47, /* VMN0 */
361 	0x56, /* VMN1 */
362 	0x65, /* VMN2 */
363 	0x65, /* VMN3 */
364 	0x6E, /* VMN4 */
365 	0x81, /* VMN5 */
366 	0x87, /* VMN6 */
367 	0x8B, /* VMN7 */
368 	0x98, /* VMN8 */
369 	0x9D, /* VMN9 */
370 	0x99, /* VMN10 */
371 	0xA8, /* VMN11 */
372 	0xBA, /* VMN12 */
373 	0x5D, /* VLN0 */
374 	0x5D, /* VLN1 */
375 	0x62, /* VLN2 */
376 	0x67, /* VLN3 */
377 	0x6B, /* VLN4 */
378 	0x72, /* VLN5 */
379 	0x7F, /* VLN6 */
380 	0x7F  /* VLN7 */
383 const uint8_t hx8394_cmd1[] = {0xC0U, 0x1FU, 0x31U};
390 const uint8_t hx8394_cmd2[] = {0xD4, 0x2};
393 	0xD8U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU,
394 	0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU,
395 	0xFFU
398 const uint8_t hx8394_bank1[] = {0xB1U, 0x00U};
401 	0xBFU, 0x40U, 0x81U, 0x50U,
402 	0x00U, 0x1AU, 0xFCU, 0x01
405 const uint8_t hx8394_cmd3[] = {0xC6U, 0xEDU};
420 	case 0U:  in hx8394_mipi_tx()
446 	return 0;  in hx8394_write()
465 		return gpio_pin_set_dt(&config->bl_gpio, 0);  in hx8394_blanking_on()
477 		return 0;  in hx8394_set_pixel_format()
487 	uint8_t param[2] = {0};  in hx8394_set_orientation()
493 	param[0] = HX8394_SET_ADDRESS;  in hx8394_set_orientation()
503 		param[1] = 0;  in hx8394_set_orientation()
519 	memset(capabilities, 0, sizeof(struct display_capabilities));  in hx8394_get_capabilities()
554 		0xB2U, 0xC0U};  in hx8394_init()
562 	if (ret < 0) {  in hx8394_init()
575 		if (ret < 0) {  in hx8394_init()
579 		gpio_pin_set_dt(&config->reset_gpio, 0);  in hx8394_init()
593 	if (ret < 0) {  in hx8394_init()
601 	if (ret < 0) {  in hx8394_init()
608 	if (ret < 0) {  in hx8394_init()
615 	if (ret < 0) {  in hx8394_init()
622 	if (ret < 0) {  in hx8394_init()
629 	if (ret < 0) {  in hx8394_init()
636 	if (ret < 0) {  in hx8394_init()
644 	if (ret < 0) {  in hx8394_init()
651 	if (ret < 0) {  in hx8394_init()
663 	if (ret < 0) {  in hx8394_init()
670 	if (ret < 0) {  in hx8394_init()
679 	if (ret < 0) {  in hx8394_init()
686 	if (ret < 0) {  in hx8394_init()
695 	if (ret < 0) {  in hx8394_init()
700 	param[0] = HX8394_SETBANK;  in hx8394_init()
701 	param[1] = 0x2;  in hx8394_init()
704 	if (ret < 0) {  in hx8394_init()
709 	if (ret < 0) {  in hx8394_init()
712 	param[1] = 0x0;  in hx8394_init()
715 	if (ret < 0) {  in hx8394_init()
719 	param[1] = 0x1;  in hx8394_init()
722 	if (ret < 0) {  in hx8394_init()
727 	if (ret < 0) {  in hx8394_init()
730 	/* Select bank 0 */  in hx8394_init()
731 	param[1] = 0x0;  in hx8394_init()
734 	if (ret < 0) {  in hx8394_init()
739 	if (ret < 0) {  in hx8394_init()
748 	if (ret < 0) {  in hx8394_init()
754 	if (ret < 0) {  in hx8394_init()
758 	param[0] = MIPI_DCS_EXIT_SLEEP_MODE;  in hx8394_init()
762 	if (ret < 0) {  in hx8394_init()
768 	param[0] = MIPI_DCS_SET_DISPLAY_ON;  in hx8394_init()
774 		if (ret < 0) {  in hx8394_init()
786 		.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(id, reset_gpios, {0}),	\
787 		.bl_gpio = GPIO_DT_SPEC_INST_GET_OR(id, bl_gpios, {0}),		\
788 		.num_of_lanes = DT_INST_PROP_BY_IDX(id, data_lanes, 0),		\