Lines Matching full:cc
62 uint32_t cc, csts; in nvme_controller_disable() local
66 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_disable()
71 enabled = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; in nvme_controller_disable()
89 cc &= ~NVME_CC_REG_EN_MASK; in nvme_controller_disable()
90 nvme_mmio_write_4(regs, cc, cc); in nvme_controller_disable()
100 uint32_t cc, csts; in nvme_controller_enable() local
103 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_enable()
108 enabled = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; in nvme_controller_enable()
124 /* Initialization values for CC */ in nvme_controller_enable()
125 cc = 0; in nvme_controller_enable()
126 cc |= 1 << NVME_CC_REG_EN_SHIFT; in nvme_controller_enable()
127 cc |= 0 << NVME_CC_REG_CSS_SHIFT; in nvme_controller_enable()
128 cc |= 0 << NVME_CC_REG_AMS_SHIFT; in nvme_controller_enable()
129 cc |= 0 << NVME_CC_REG_SHN_SHIFT; in nvme_controller_enable()
130 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */ in nvme_controller_enable()
131 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */ in nvme_controller_enable()
132 cc |= nvme_ctrlr->mps << NVME_CC_REG_MPS_SHIFT; in nvme_controller_enable()
134 nvme_mmio_write_4(regs, cc, cc); in nvme_controller_enable()