3  * SPDX-License-Identifier: Apache-2.0
51 /* used to convert the clock-names property into an array of clock names */
72 /* used to convert a clock-names property into an array of clock names. If the
89 /* used to parse the tx-fifo-watermark property. If said property is not
97 /* used to parse the rx-fifo-watermark property. If said property is not
107 	POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[idx]))
111 	POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[idx]))
113 /* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */
117 /* used to retrieve the TX/RX FIFO's size (in FIFO words) */
129 /* used to retrieve the synchronization mode of the transmitter. If this
130  * property is not specified, ASYNC mode will be used.
135 /* used to retrieve the synchronization mode of the receiver. If this property
136  * is not specified, ASYNC mode will be used.
173  * When enabling the SYNC component, the ASYNC component will also be enabled.
174  * Attempting to disable the SYNC component will fail unless the SYNC bit is
190 	((dir) == DAI_DIR_RX ? (UINT_TO_I2S(regmap)->RCSR & I2S_RCSR_RE_MASK) : \
191 	 (UINT_TO_I2S(regmap)->TCSR & I2S_TCSR_TE_MASK))
210 	((dir) == DAI_DIR_RX ? ((UINT_TO_I2S(regmap))->RCSR & (which)) : \
211 	 ((UINT_TO_I2S(regmap))->TCSR & (which)))
218 /* used to retrieve the SYNC direction. Use this macro when you know for sure
219  * you have 1 SYNC direction with 1 ASYNC direction.
222 	((cfg)->tx_sync_mode == kSAI_ModeSync ? DAI_DIR_TX : DAI_DIR_RX)
225  * you have 1 SYNC direction with 1 ASYNC direction.
228 	((cfg)->tx_sync_mode == kSAI_ModeAsync ? DAI_DIR_TX : DAI_DIR_RX)
232 	((dir) == DAI_DIR_TX ? data->tx_enabled : data->rx_enabled)
238 	((dir) == DAI_DIR_TX ? BIT((cfg)->tx_dline) : BIT((cfg)->rx_dline))
265 	/* if the tx/rx-fifo-watermark properties are not specified, it's going
274 	/* RX synchronization mode - may be SYNC or ASYNC */
276 	/* TX synchronization mode - may be SYNC or ASYNC */
292 	/* CLOCK-related data */
297 	/* TDM-related data */
319 		return -EINVAL;  in get_msel()
327 	UINT_TO_I2S(regmap)->MCR &= ~SAI_MCLK_MCR_MSEL_MASK;  in set_msel()
328 	UINT_TO_I2S(regmap)->MCR |= msel;  in set_msel()
335 	for (i = 0; i < clk_data->clock_num; i++) {  in clk_lookup_by_name()
336 		if (!strcmp(name, clk_data->clock_names[i])) {  in clk_lookup_by_name()
341 	return -EINVAL;  in clk_lookup_by_name()
363 		return -EINVAL;  in get_mclk_rate()
372 	return clock_control_get_rate(clk_data->dev,  in get_mclk_rate()
373 				      UINT_TO_POINTER(clk_data->clocks[clk_idx]),  in get_mclk_rate()
385 	 *	2) BCLK uses MCLK1 source. (only applicable to master mode)  in get_bclk_default_config()
389 	cfg->bclkPolarity = kSAI_PolarityActiveHigh;  in get_bclk_default_config()
390 	cfg->bclkSource = kSAI_BclkSourceMclkOption1;  in get_bclk_default_config()
403 	cfg->frameSyncEarly = true;  in get_fsync_default_config()
404 	cfg->frameSyncPolarity = kSAI_PolarityActiveHigh;  in get_fsync_default_config()
413 	 * 1) Data pin is not tri-stated.  in get_serial_default_config()
418 	cfg->dataMode = kSAI_DataPinStateOutputZero;  in get_serial_default_config()
420 	cfg->dataOrder = kSAI_DataMSB;  in get_serial_default_config()
432 		return data->rx_state;  in sai_get_state()
434 		return data->tx_state;  in sai_get_state()
450 		return -EPERM;  in sai_update_state()
455 			return -EPERM;  in sai_update_state()
462 			return -EPERM;  in sai_update_state()
467 			return -EPERM;  in sai_update_state()
474 			return -EPERM;  in sai_update_state()
483 		return -EINVAL;  in sai_update_state()
487 		data->rx_state = new_state;  in sai_update_state()
489 		data->tx_state = new_state;  in sai_update_state()
501 		base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK));  in sai_tx_rx_force_disable()
503 		base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK));  in sai_tx_rx_force_disable()
512 		data->rx_enabled = enable;  in sai_tx_rx_sw_enable_disable()
514 		data->tx_enabled = enable;  in sai_tx_rx_sw_enable_disable()
540 		base->RCR3 &= ~I2S_RCR3_RCE_MASK;  in sai_tx_rx_set_dline_mask()
541 		base->RCR3 |= I2S_RCR3_RCE(mask);  in sai_tx_rx_set_dline_mask()
543 		base->TCR3 &= ~I2S_TCR3_TCE_MASK;  in sai_tx_rx_set_dline_mask()
544 		base->TCR3 |= I2S_TCR3_TCE(mask);  in sai_tx_rx_set_dline_mask()
552 	LOG_DBG("TCSR: 0x%x", base->TCSR);  in sai_dump_register_data()
553 	LOG_DBG("RCSR: 0x%x", base->RCSR);  in sai_dump_register_data()
555 	LOG_DBG("TCR1: 0x%x", base->TCR1);  in sai_dump_register_data()
556 	LOG_DBG("RCR1: 0x%x", base->RCR1);  in sai_dump_register_data()
558 	LOG_DBG("TCR2: 0x%x", base->TCR2);  in sai_dump_register_data()
559 	LOG_DBG("RCR2: 0x%x", base->RCR2);  in sai_dump_register_data()
561 	LOG_DBG("TCR3: 0x%x", base->TCR3);  in sai_dump_register_data()
562 	LOG_DBG("RCR3: 0x%x", base->RCR3);  in sai_dump_register_data()
564 	LOG_DBG("TCR4: 0x%x", base->TCR4);  in sai_dump_register_data()
565 	LOG_DBG("RCR4: 0x%x", base->RCR4);  in sai_dump_register_data()
567 	LOG_DBG("TCR5: 0x%x", base->TCR5);  in sai_dump_register_data()
568 	LOG_DBG("RCR5: 0x%x", base->RCR5);  in sai_dump_register_data()
570 	LOG_DBG("TMR: 0x%x", base->TMR);  in sai_dump_register_data()
571 	LOG_DBG("RMR: 0x%x", base->RMR);  in sai_dump_register_data()
574 	LOG_DBG("MCR: 0x%x", base->MCR);  in sai_dump_register_data()