31 #define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)  argument
32 #define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)  argument
37 #define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
41 #define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)  argument
46 #define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)  argument
47 #define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)  argument
55 #define SSCR1_SPO		BIT(3)
59 #define SSCR1_TFT(x)		DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)  argument
61 #define SSCR1_RFT(x)		DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)  argument
81 #define SSCR2_PSPSRWFDFD	BIT(3)
93 #define SSSR_RNE		BIT(3)
101 #define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)  argument
102 #define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)  argument
103 #define SSPSP_ETDS		BIT(3)
104 #define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)  argument
105 #define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)  argument
106 #define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)  argument
107 #define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)  argument
108 #define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)  argument
112 #define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)  argument
122 #define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)  argument
123 #define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))  argument
127 #define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)  argument
128 #define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))  argument
134 #define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)  argument
135 #define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
146 #define SSCR4_TOT_FRM_PRD(x)	((x) << 7)  argument
149 #define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)  argument
150 #define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)  argument
153 #define SFIFOTT_TX(x)		((x) - 1)  argument
154 #define SFIFOTT_RX(x)		(((x) - 1) << 16)  argument
157 #define SFIFOL_TFL(x)		((x) & 0xFFFF)  argument
158 #define SFIFOL_RFL(x)		((x) >> 16)  argument
167 #define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)  argument
168 #define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)  argument
188 #define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)  argument
201 #define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)  argument
212 #define SSP_CLK_BCLK_ACTIVE	BIT(3)
216 #define I2SLCTL_SPA(x)		BIT(16 + x)  argument
217 #define I2SLCTL_CPA(x)		BIT(23 + x)  argument
221 #define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(29, 27, x)  argument
223 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)  argument
224 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)  argument
229 /** \brief Offset of MCLK Divider x Ratio Register. */
230 #define MN_MDIVR(x) (0x180 + (x) * 0x4)  argument
233 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)  argument
236 #define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)  argument
238 /** \brief Offset of BCLK x M/N Divider M Value Register. */
239 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)  argument
241 /** \brief Offset of BCLK x M/N Divider N Value Register. */
242 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)  argument
245 #define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)  argument