26 static inline void dai_dmic_write(const struct dai_intel_dmic *dmic,  in dai_dmic_write()  argument
29 	sys_write32(val, dmic->reg_base + reg);  in dai_dmic_write()
32 static inline uint32_t dai_dmic_read(const struct dai_intel_dmic *dmic, uint32_t reg)  in dai_dmic_read()  argument
34 	return sys_read32(dmic->reg_base + reg);  in dai_dmic_read()
57 static void dai_dmic_write_coeff(const struct dai_intel_dmic *dmic, uint32_t base,  in dai_dmic_write_coeff()  argument
65 			dai_dmic_write(dmic, base, *coeff++);  in dai_dmic_write_coeff()
76 			dai_dmic_write(dmic, base, coeff_val);  in dai_dmic_write_coeff()
89 static const uint32_t *dai_dmic_configure_coeff(const struct dai_intel_dmic *dmic,  in dai_dmic_configure_coeff()  argument
118 	if (dmic->dai_config_params.dai_index == 0) {  in dai_dmic_configure_coeff()
119 		dai_dmic_write_coeff(dmic, pdm_base + PDM_COEFFICIENT_A, coeffs, fir_length_a,  in dai_dmic_configure_coeff()
122 		dai_dmic_write_coeff(dmic, pdm_base + PDM_COEFFICIENT_B, coeffs_b, fir_length_b,  in dai_dmic_configure_coeff()
129 static int dai_nhlt_get_clock_div(const struct dai_intel_dmic *dmic, const int pdm)  in dai_nhlt_get_clock_div()  argument
134 	val = dai_dmic_read(dmic, dmic_base[pdm] + CIC_CONFIG);  in dai_nhlt_get_clock_div()
137 	val = dai_dmic_read(dmic, dmic_base[pdm] + MIC_CONTROL);  in dai_nhlt_get_clock_div()
140 	val = dai_dmic_read(dmic, dmic_base[pdm] +  in dai_nhlt_get_clock_div()
141 			    FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index + FIR_CONFIG);  in dai_nhlt_get_clock_div()
148 		dmic->dai_config_params.dai_index, rate_div, p_clkdiv, p_mcic, p_mfir);  in dai_nhlt_get_clock_div()
158 static int dai_nhlt_update_rate(struct dai_intel_dmic *dmic, const int clock_source, const int pdm)  in dai_nhlt_update_rate()  argument
162 	rate_div = dai_nhlt_get_clock_div(dmic, pdm);  in dai_nhlt_update_rate()
167 	dmic->dai_config_params.rate = adsp_clock_source_frequency(clock_source) /  in dai_nhlt_update_rate()
171 		dmic->dai_config_params.rate, dmic->dai_config_params.channels,  in dai_nhlt_update_rate()
172 		dmic->dai_config_params.format);  in dai_nhlt_update_rate()
179 static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic,  in dai_ipm_source_to_enable()  argument
192 						dmic, dmic_base[source_pdm] + MIC_CONTROL));  in dai_ipm_source_to_enable()
194 			dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */  in dai_ipm_source_to_enable()
196 			dmic->enable[source_pdm] = mic_swap ? 0x2 : 0x1; /* PDMi MIC B or MIC A */  in dai_ipm_source_to_enable()
203 static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int clock_source)  in dai_nhlt_dmic_dai_params_get()  argument
211 	uint32_t outcontrol_val = dai_dmic_read(dmic, dmic->dai_config_params.dai_index *  in dai_nhlt_dmic_dai_params_get()
217 		dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;  in dai_nhlt_dmic_dai_params_get()
218 		dmic->dai_config_params.word_size = 16;  in dai_nhlt_dmic_dai_params_get()
221 		dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE;  in dai_nhlt_dmic_dai_params_get()
222 		dmic->dai_config_params.word_size = 32;  in dai_nhlt_dmic_dai_params_get()
238 	dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm;  in dai_nhlt_dmic_dai_params_get()
240 		dmic->enable[n] = 0;  in dai_nhlt_dmic_dai_params_get()
246 	ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);  in dai_nhlt_dmic_dai_params_get()
253 	ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);  in dai_nhlt_dmic_dai_params_get()
260 	ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);  in dai_nhlt_dmic_dai_params_get()
267 	ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);  in dai_nhlt_dmic_dai_params_get()
273 	return dai_nhlt_update_rate(dmic, clock_source, first_pdm);  in dai_nhlt_dmic_dai_params_get()
282 static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)  in dai_dmic_clock_select_set()  argument
286 	val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_clock_select_set()
289 	sys_write32(val, dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_clock_select_set()
291 	val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_clock_select_set()
294 	sys_write32(val, dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_clock_select_set()
303 static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic)  in dai_dmic_clock_select_get()  argument
307 	val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_clock_select_get()
310 	val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_clock_select_get()
320 static int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t clock_source)  in dai_dmic_set_clock()  argument
329 	if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) {  in dai_dmic_set_clock()
334 	dai_dmic_clock_select_set(dmic, clock_source);  in dai_dmic_set_clock()
338 static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic)  in dai_nhlt_dmic_dai_params_get()  argument
347 	outcontrol = dai_dmic_read(dmic, dmic->dai_config_params.dai_index * PDM_CHANNEL_REGS_SIZE +  in dai_nhlt_dmic_dai_params_get()
353 		dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;  in dai_nhlt_dmic_dai_params_get()
356 		dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE;  in dai_nhlt_dmic_dai_params_get()
363 	fir_control[0] = dai_dmic_read(dmic, dmic_base[0] +  in dai_nhlt_dmic_dai_params_get()
364 				       dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE +  in dai_nhlt_dmic_dai_params_get()
367 	fir_control[1] = dai_dmic_read(dmic, dmic_base[1] +  in dai_nhlt_dmic_dai_params_get()
368 				       dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE +  in dai_nhlt_dmic_dai_params_get()
371 	mic_control[0] = dai_dmic_read(dmic, dmic_base[0] + MIC_CONTROL);  in dai_nhlt_dmic_dai_params_get()
372 	mic_control[1] = dai_dmic_read(dmic, dmic_base[1] + MIC_CONTROL);  in dai_nhlt_dmic_dai_params_get()
378 			dmic->dai_config_params.channels = 2;  in dai_nhlt_dmic_dai_params_get()
379 			dmic->enable[0] = 0x3; /* PDM0 MIC A and B */  in dai_nhlt_dmic_dai_params_get()
380 			dmic->enable[1] = 0x0;	/* PDM1 none */  in dai_nhlt_dmic_dai_params_get()
383 			dmic->dai_config_params.channels = 1;  in dai_nhlt_dmic_dai_params_get()
385 			dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */  in dai_nhlt_dmic_dai_params_get()
386 			dmic->enable[1] = 0x0;	/* PDM1 */  in dai_nhlt_dmic_dai_params_get()
392 			dmic->dai_config_params.channels = 2;  in dai_nhlt_dmic_dai_params_get()
393 			dmic->enable[0] = 0x0; /* PDM0 none */  in dai_nhlt_dmic_dai_params_get()
394 			dmic->enable[1] = 0x3;	/* PDM1 MIC A and B */  in dai_nhlt_dmic_dai_params_get()
396 			dmic->dai_config_params.channels = 1;  in dai_nhlt_dmic_dai_params_get()
397 			dmic->enable[0] = 0x0; /* PDM0 none */  in dai_nhlt_dmic_dai_params_get()
399 			dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */  in dai_nhlt_dmic_dai_params_get()
406 			dmic->dai_config_params.channels = 4;  in dai_nhlt_dmic_dai_params_get()
407 			dmic->enable[0] = 0x3; /* PDM0 MIC A and B */  in dai_nhlt_dmic_dai_params_get()
408 			dmic->enable[1] = 0x3;	/* PDM1 MIC A and B */  in dai_nhlt_dmic_dai_params_get()
420 	return dai_nhlt_update_rate(dmic, 0, 0);  in dai_nhlt_dmic_dai_params_get()
423 static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t clock_source)  in dai_dmic_set_clock()  argument
603 static void configure_fir(struct dai_intel_dmic *dmic, const uint32_t base,  in configure_fir()  argument
612 	dai_dmic_write(dmic, base + FIR_CONFIG, val);  in configure_fir()
619 	dai_dmic_write(dmic, base + FIR_CONTROL, val);  in configure_fir()
623 	dai_dmic_write(dmic, base + DC_OFFSET_LEFT, fir_cfg->dc_offset_left);  in configure_fir()
624 	dai_dmic_write(dmic, base + DC_OFFSET_RIGHT, fir_cfg->dc_offset_right);  in configure_fir()
625 	dai_dmic_write(dmic, base + OUT_GAIN_LEFT, fir_cfg->out_gain_left);  in configure_fir()
626 	dai_dmic_write(dmic, base + OUT_GAIN_RIGHT, fir_cfg->out_gain_right);  in configure_fir()
628 	dmic->gain_left = fir_cfg->out_gain_left;  in configure_fir()
629 	dmic->gain_right = fir_cfg->out_gain_right;  in configure_fir()
632 int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cfg)  in dai_dmic_set_config_nhlt()  argument
654 	if (dmic->dai_config_params.dai_index >= DMIC_HW_FIFOS_MAX) {  in dai_dmic_set_config_nhlt()
656 			 dmic->dai_config_params.dai_index);  in dai_dmic_set_config_nhlt()
673 	ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source);  in dai_dmic_set_config_nhlt()
695 		if (dmic->dai_config_params.dai_index == n) {  in dai_dmic_set_config_nhlt()
703 			dai_dmic_write(dmic, dmic->dai_config_params.dai_index *  in dai_dmic_set_config_nhlt()
706 			LOG_INF("OUTCONTROL%d = %08x", dmic->dai_config_params.dai_index,  in dai_dmic_set_config_nhlt()
713 			dmic->fifo.depth = 1 << val;  in dai_dmic_set_config_nhlt()
736 			dai_dmic_write(dmic, pdm_base + CIC_CONTROL, CIC_CONTROL_MIC_MUTE);  in dai_dmic_set_config_nhlt()
751 			dai_dmic_write(dmic, pdm_base + CIC_CONTROL, val);  in dai_dmic_set_config_nhlt()
756 			dai_dmic_write(dmic, pdm_base + CIC_CONFIG, val);  in dai_dmic_set_config_nhlt()
761 			dai_dmic_write(dmic, pdm_base + MIC_CONTROL, val);  in dai_dmic_set_config_nhlt()
765 		configure_fir(dmic, pdm_base +  in dai_dmic_set_config_nhlt()
766 			      FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index,  in dai_dmic_set_config_nhlt()
767 			      &pdm_cfg->fir_config[dmic->dai_config_params.dai_index]);  in dai_dmic_set_config_nhlt()
794 		fir_coeffs = dai_dmic_configure_coeff(dmic, pdm_cfg, pdm_base, fir_coeffs);  in dai_dmic_set_config_nhlt()
806 	ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source);  in dai_dmic_set_config_nhlt()
808 	ret = dai_nhlt_dmic_dai_params_get(dmic);  in dai_dmic_set_config_nhlt()
815 		dmic->enable[0], dmic->enable[1]);  in dai_dmic_set_config_nhlt()