Lines Matching +full:decimation +full:- +full:rate
4 * SPDX-License-Identifier: Apache-2.0
29 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
34 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
64 while (length--) { in dai_dmic_write_coeff()
71 while (length--) { in dai_dmic_write_coeff()
98 fir_length_a = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[0].fir_config) + 1; in dai_dmic_configure_coeff()
99 fir_length_b = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[1].fir_config) + 1; in dai_dmic_configure_coeff()
109 /* First dword is not included into length_0 and length_1 - skip it. */ in dai_dmic_configure_coeff()
118 if (dmic->dai_config_params.dai_index == 0) { in dai_dmic_configure_coeff()
141 FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index + FIR_CONFIG); in dai_nhlt_get_clock_div()
148 dmic->dai_config_params.dai_index, rate_div, p_clkdiv, p_mcic, p_mfir); in dai_nhlt_get_clock_div()
151 LOG_ERR("zero clock divide or decimation factor"); in dai_nhlt_get_clock_div()
152 return -EINVAL; in dai_nhlt_get_clock_div()
167 dmic->dai_config_params.rate = adsp_clock_source_frequency(clock_source) / in dai_nhlt_update_rate()
170 LOG_INF("rate = %d, channels = %d, format = %d", in dai_nhlt_update_rate()
171 dmic->dai_config_params.rate, dmic->dai_config_params.channels, in dai_nhlt_update_rate()
172 dmic->dai_config_params.format); in dai_nhlt_update_rate()
186 return -EINVAL; in dai_ipm_source_to_enable()
194 dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */ in dai_ipm_source_to_enable()
196 dmic->enable[source_pdm] = mic_swap ? 0x2 : 0x1; /* PDMi MIC B or MIC A */ in dai_ipm_source_to_enable()
211 uint32_t outcontrol_val = dai_dmic_read(dmic, dmic->dai_config_params.dai_index * in dai_nhlt_dmic_dai_params_get()
217 dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE; in dai_nhlt_dmic_dai_params_get()
218 dmic->dai_config_params.word_size = 16; in dai_nhlt_dmic_dai_params_get()
221 dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE; in dai_nhlt_dmic_dai_params_get()
222 dmic->dai_config_params.word_size = 32; in dai_nhlt_dmic_dai_params_get()
226 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
233 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
238 dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm; in dai_nhlt_dmic_dai_params_get()
240 dmic->enable[n] = 0; in dai_nhlt_dmic_dai_params_get()
249 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
256 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
263 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
270 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
286 val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_clock_select_set()
289 sys_write32(val, dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_clock_select_set()
291 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()
294 sys_write32(val, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()
307 val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_clock_select_get()
310 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_get()
325 return -ENOTSUP; in dai_dmic_set_clock()
329 if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) { in dai_dmic_set_clock()
330 return -ENOTSUP; in dai_dmic_set_clock()
347 outcontrol = dai_dmic_read(dmic, dmic->dai_config_params.dai_index * PDM_CHANNEL_REGS_SIZE + in dai_nhlt_dmic_dai_params_get()
353 dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE; in dai_nhlt_dmic_dai_params_get()
356 dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE; in dai_nhlt_dmic_dai_params_get()
360 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
364 dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE + in dai_nhlt_dmic_dai_params_get()
368 dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE + in dai_nhlt_dmic_dai_params_get()
378 dmic->dai_config_params.channels = 2; in dai_nhlt_dmic_dai_params_get()
379 dmic->enable[0] = 0x3; /* PDM0 MIC A and B */ in dai_nhlt_dmic_dai_params_get()
380 dmic->enable[1] = 0x0; /* PDM1 none */ in dai_nhlt_dmic_dai_params_get()
383 dmic->dai_config_params.channels = 1; in dai_nhlt_dmic_dai_params_get()
385 dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */ in dai_nhlt_dmic_dai_params_get()
386 dmic->enable[1] = 0x0; /* PDM1 */ in dai_nhlt_dmic_dai_params_get()
392 dmic->dai_config_params.channels = 2; in dai_nhlt_dmic_dai_params_get()
393 dmic->enable[0] = 0x0; /* PDM0 none */ in dai_nhlt_dmic_dai_params_get()
394 dmic->enable[1] = 0x3; /* PDM1 MIC A and B */ in dai_nhlt_dmic_dai_params_get()
396 dmic->dai_config_params.channels = 1; in dai_nhlt_dmic_dai_params_get()
397 dmic->enable[0] = 0x0; /* PDM0 none */ in dai_nhlt_dmic_dai_params_get()
399 dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */ in dai_nhlt_dmic_dai_params_get()
406 dmic->dai_config_params.channels = 4; in dai_nhlt_dmic_dai_params_get()
407 dmic->enable[0] = 0x3; /* PDM0 MIC A and B */ in dai_nhlt_dmic_dai_params_get()
408 dmic->enable[1] = 0x3; /* PDM1 MIC A and B */ in dai_nhlt_dmic_dai_params_get()
412 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
417 return -EINVAL; in dai_nhlt_dmic_dai_params_get()
450 return -EINVAL; in print_outcontrol()
496 bf7 = -1; in print_cic_control()
529 bf3 = -1; in print_fir_control()
557 LOG_DBG("CIC_CONTROL = %08x", pdm_cfg->cic_control); in print_pdm_ctrl()
559 val = pdm_cfg->cic_config; in print_pdm_ctrl()
565 val = pdm_cfg->mic_control; in print_pdm_ctrl()
570 bf1 = -1; in print_pdm_ctrl()
586 val = fir_cfg->fir_config; in print_fir_config()
594 print_fir_control(fir_cfg->fir_control); in print_fir_config()
597 LOG_DBG("DC_OFFSET_LEFT = %08x", fir_cfg->dc_offset_left); in print_fir_config()
598 LOG_DBG("DC_OFFSET_RIGHT = %08x", fir_cfg->dc_offset_right); in print_fir_config()
599 LOG_DBG("OUT_GAIN_LEFT = %08x", fir_cfg->out_gain_left); in print_fir_config()
600 LOG_DBG("OUT_GAIN_RIGHT = %08x", fir_cfg->out_gain_right); in print_fir_config()
611 val = fir_cfg->fir_config; in configure_fir()
614 val = fir_cfg->fir_control; in configure_fir()
623 dai_dmic_write(dmic, base + DC_OFFSET_LEFT, fir_cfg->dc_offset_left); in configure_fir()
624 dai_dmic_write(dmic, base + DC_OFFSET_RIGHT, fir_cfg->dc_offset_right); in configure_fir()
625 dai_dmic_write(dmic, base + OUT_GAIN_LEFT, fir_cfg->out_gain_left); in configure_fir()
626 dai_dmic_write(dmic, base + OUT_GAIN_RIGHT, fir_cfg->out_gain_right); in configure_fir()
628 dmic->gain_left = fir_cfg->out_gain_left; in configure_fir()
629 dmic->gain_right = fir_cfg->out_gain_right; in configure_fir()
654 if (dmic->dai_config_params.dai_index >= DMIC_HW_FIFOS_MAX) { in dai_dmic_set_config_nhlt()
656 dmic->dai_config_params.dai_index); in dai_dmic_set_config_nhlt()
657 return -EINVAL; in dai_dmic_set_config_nhlt()
667 channel_ctrl_mask = dmic_cfg->channel_ctrl_mask; in dai_dmic_set_config_nhlt()
673 ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source); in dai_dmic_set_config_nhlt()
681 return -EINVAL; in dai_dmic_set_config_nhlt()
695 if (dmic->dai_config_params.dai_index == n) { in dai_dmic_set_config_nhlt()
703 dai_dmic_write(dmic, dmic->dai_config_params.dai_index * in dai_dmic_set_config_nhlt()
706 LOG_INF("OUTCONTROL%d = %08x", dmic->dai_config_params.dai_index, in dai_dmic_set_config_nhlt()
713 dmic->fifo.depth = 1 << val; in dai_dmic_set_config_nhlt()
720 pdm_ctrl_mask = ((const struct nhlt_pdm_ctrl_mask *)p)->pdm_ctrl_mask; in dai_dmic_set_config_nhlt()
726 return -EINVAL; in dai_dmic_set_config_nhlt()
746 val = pdm_cfg->cic_control; in dai_dmic_set_config_nhlt()
755 val = pdm_cfg->cic_config; in dai_dmic_set_config_nhlt()
759 val = pdm_cfg->mic_control; in dai_dmic_set_config_nhlt()
766 FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index, in dai_dmic_set_config_nhlt()
767 &pdm_cfg->fir_config[dmic->dai_config_params.dai_index]); in dai_dmic_set_config_nhlt()
773 if (pdm_cfg->reuse_fir_from_pdm == 0) { in dai_dmic_set_config_nhlt()
775 fir_coeffs = pdm_cfg->fir_coeffs; in dai_dmic_set_config_nhlt()
780 if (pdm_cfg->reuse_fir_from_pdm > pdm_idx) { in dai_dmic_set_config_nhlt()
781 LOG_ERR("invalid reuse fir index %u", pdm_cfg->reuse_fir_from_pdm); in dai_dmic_set_config_nhlt()
782 return -EINVAL; in dai_dmic_set_config_nhlt()
786 fir_coeffs = pdm_coeff_ptr[pdm_cfg->reuse_fir_from_pdm - 1]; in dai_dmic_set_config_nhlt()
789 LOG_ERR("unable to reuse fir from %u", pdm_cfg->reuse_fir_from_pdm); in dai_dmic_set_config_nhlt()
790 return -EINVAL; in dai_dmic_set_config_nhlt()
797 if (pdm_cfg->reuse_fir_from_pdm) { in dai_dmic_set_config_nhlt()
799 pdm_cfg = (const struct nhlt_pdm_ctrl_cfg *)&pdm_cfg->fir_coeffs; in dai_dmic_set_config_nhlt()
806 ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source); in dai_dmic_set_config_nhlt()
815 dmic->enable[0], dmic->enable[1]); in dai_dmic_set_config_nhlt()