28 static const uint32_t dmic_base[4] = {PDM0, PDM1, PDM2, PDM3};  variable
527 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_gain_ramp()
532 			dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
539 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
541 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
544 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
547 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
569 		dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0);  in dai_dmic_start()
596 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
601 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
607 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
610 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
614 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
617 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
622 		dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_start()
633 		dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
637 			dai_dmic_read(dmic, dmic_base[i] + CIC_CONTROL));  in dai_dmic_start()
682 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_stop()
688 		dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_stop()