37 int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *spec_config);
119 static void dai_dmic_update_bits(const struct dai_intel_dmic *dmic,  in dai_dmic_update_bits()  argument
122 	uint32_t dest = dmic->reg_base + reg;  in dai_dmic_update_bits()
127 static inline void dai_dmic_write(const struct dai_intel_dmic *dmic,  in dai_dmic_write()  argument
130 	sys_write32(val, dmic->reg_base + reg);  in dai_dmic_write()
133 static inline uint32_t dai_dmic_read(const struct dai_intel_dmic *dmic,  in dai_dmic_read()  argument
136 	return sys_read32(dmic->reg_base + reg);  in dai_dmic_read()
140 static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic)  in dai_dmic_claim_ownership()  argument
143 	sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) |  in dai_dmic_claim_ownership()
144 		    FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_claim_ownership()
147 static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)  in dai_dmic_release_ownership()  argument
150 	sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) &  in dai_dmic_release_ownership()
151 			~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_release_ownership()
156 static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic) {}  in dai_dmic_claim_ownership()  argument
157 static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) {}  in dai_dmic_release_ownership()  argument
161 static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)  in dai_dmic_base()  argument
164 	return dmic->hdamldmic_base;  in dai_dmic_base()
166 	return dmic->shim_base;  in dai_dmic_base()
171 static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic)  in dai_dmic_set_sync_period()  argument
174 	uint32_t base = dai_dmic_base(dmic);  in dai_dmic_set_sync_period()
197 static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic)  in dai_dmic_clear_sync_period()  argument
199 	uint32_t base = dai_dmic_base(dmic);  in dai_dmic_clear_sync_period()
208 static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic)  in dai_dmic_sync_prepare()  argument
210 	uint32_t base = dai_dmic_base(dmic);  in dai_dmic_sync_prepare()
217 static void dmic_sync_trigger(const struct dai_intel_dmic *dmic)  in dmic_sync_trigger()  argument
219 	uint32_t base = dai_dmic_base(dmic);  in dmic_sync_trigger()
235 static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic) {}  in dai_dmic_set_sync_period()  argument
236 static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic) {}  in dai_dmic_clear_sync_period()  argument
237 static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic) {}  in dai_dmic_sync_prepare()  argument
238 static void dmic_sync_trigger(const struct dai_intel_dmic *dmic) {}  in dmic_sync_trigger()  argument
242 static void dai_dmic_start_fifo_packers(struct dai_intel_dmic *dmic, int fifo_index)  in dai_dmic_start_fifo_packers()  argument
246 	dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,  in dai_dmic_start_fifo_packers()
251 static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,  in dai_dmic_stop_fifo_packers()  argument
255 	dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,  in dai_dmic_stop_fifo_packers()
265 	struct dai_intel_dmic *dmic = ((struct device *)data)->data;  in dai_dmic_irq_handler()  local
270 	val0 = dai_dmic_read(dmic, OUTSTAT);  in dai_dmic_irq_handler()
271 	val1 = dai_dmic_read(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE);  in dai_dmic_irq_handler()
276 		dai_dmic_write(dmic, OUTSTAT, val0);  in dai_dmic_irq_handler()
277 		dai_dmic_stop_fifo_packers(dmic, 0);  in dai_dmic_irq_handler()
282 		dai_dmic_write(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE, val1);  in dai_dmic_irq_handler()
283 		dai_dmic_stop_fifo_packers(dmic, 1);  in dai_dmic_irq_handler()
287 static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)  in dai_dmic_dis_clk_gating()  argument
291 	sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),  in dai_dmic_dis_clk_gating()
292 		    dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_dis_clk_gating()
294 	sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD),  in dai_dmic_dis_clk_gating()
295 		    dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_dis_clk_gating()
299 static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)  in dai_dmic_en_clk_gating()  argument
303 	sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),  in dai_dmic_en_clk_gating()
304 		    dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_en_clk_gating()
306 	sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),  in dai_dmic_en_clk_gating()
307 		    dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_en_clk_gating()
312 static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmic,  in dai_dmic_program_channel_map()  argument
318 	uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;  in dai_dmic_program_channel_map()
322 	ARG_UNUSED(dmic);  in dai_dmic_program_channel_map()
328 static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)  in dai_dmic_en_power()  argument
330 	uint32_t base = dai_dmic_base(dmic);  in dai_dmic_en_power()
342 static inline void dai_dmic_dis_power(const struct dai_intel_dmic *dmic)  in dai_dmic_dis_power()  argument
344 	uint32_t base = dai_dmic_base(dmic);  in dai_dmic_dis_power()
350 static int dai_dmic_probe(struct dai_intel_dmic *dmic)  in dai_dmic_probe()  argument
355 	dmic->state = DAI_STATE_NOT_READY;  in dai_dmic_probe()
358 	dai_dmic_en_power(dmic);  in dai_dmic_probe()
361 	dai_dmic_dis_clk_gating(dmic);  in dai_dmic_probe()
364 	dai_dmic_set_sync_period(CONFIG_DAI_DMIC_PLATFORM_SYNC_PERIOD, dmic);  in dai_dmic_probe()
367 	dai_dmic_claim_ownership(dmic);  in dai_dmic_probe()
369 	irq_enable(dmic->irq);  in dai_dmic_probe()
374 static int dai_dmic_remove(struct dai_intel_dmic *dmic)  in dai_dmic_remove()  argument
381 	irq_disable(dmic->irq);  in dai_dmic_remove()
395 	dai_dmic_en_clk_gating(dmic);  in dai_dmic_remove()
396 	dai_dmic_dis_power(dmic);  in dai_dmic_remove()
399 	dai_dmic_clear_sync_period(dmic);  in dai_dmic_remove()
402 	dai_dmic_release_ownership(dmic);  in dai_dmic_remove()
473 static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)  in dai_dmic_gain_ramp()  argument
494 	if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {  in dai_dmic_gain_ramp()
498 	key = k_spin_lock(&dmic->lock);  in dai_dmic_gain_ramp()
503 	dmic->startcount++;  in dai_dmic_gain_ramp()
504 	dmic->gain = q_multsr_sat_32x32(dmic->gain, dmic->gain_coef, Q_SHIFT_GAIN_X_GAIN_COEF);  in dai_dmic_gain_ramp()
509 	gval = dmic->gain >> 11;  in dai_dmic_gain_ramp()
517 		dmic->gain = DMIC_HW_FIR_GAIN_MAX << 11;  in dai_dmic_gain_ramp()
522 		if (!dmic->enable[i]) {  in dai_dmic_gain_ramp()
526 		if (dmic->startcount == DMIC_UNMUTE_CIC) {  in dai_dmic_gain_ramp()
527 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_gain_ramp()
531 		if (dmic->startcount == DMIC_UNMUTE_FIR) {  in dai_dmic_gain_ramp()
532 			dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
533 					     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_gain_ramp()
539 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
540 				       dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, val);  in dai_dmic_gain_ramp()
541 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
542 				       dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, val);  in dai_dmic_gain_ramp()
544 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
545 				       dmic->dai_config_params.dai_index + OUT_GAIN_LEFT,  in dai_dmic_gain_ramp()
546 				       dmic->gain_left);  in dai_dmic_gain_ramp()
547 			dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_gain_ramp()
548 				       dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT,  in dai_dmic_gain_ramp()
549 				       dmic->gain_right);  in dai_dmic_gain_ramp()
553 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_gain_ramp()
556 static void dai_dmic_start(struct dai_intel_dmic *dmic)  in dai_dmic_start()  argument
565 	key = k_spin_lock(&dmic->lock);  in dai_dmic_start()
569 		dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0);  in dai_dmic_start()
573 	dmic->startcount = 0;  in dai_dmic_start()
576 	dmic->gain_coef = db2lin_fixed(LOGRAMP_CONST_TERM / dmic->unmute_time_ms);  in dai_dmic_start()
579 	dmic->gain = Q_SHIFT_LEFT(db2lin_fixed(LOGRAMP_START_DB), 20, 30);  in dai_dmic_start()
581 	dai_dmic_sync_prepare(dmic);  in dai_dmic_start()
583 	dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index);  in dai_dmic_start()
586 		mic_a = dmic->enable[i] & 1;  in dai_dmic_start()
587 		mic_b = (dmic->enable[i] & 2) >> 1;  in dai_dmic_start()
588 		start_fir = dmic->enable[i] > 0;  in dai_dmic_start()
596 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
601 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
607 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
610 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
614 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
617 			dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,  in dai_dmic_start()
622 		dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_start()
623 				     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_start()
633 		dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_start()
637 			dai_dmic_read(dmic, dmic_base[i] + CIC_CONTROL));  in dai_dmic_start()
642 	dai_dmic_global.active_fifos_mask |= BIT(dmic->dai_config_params.dai_index);  in dai_dmic_start()
643 	dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_start()
645 	dmic->state = DAI_STATE_RUNNING;  in dai_dmic_start()
646 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_start()
648 	dmic_sync_trigger(dmic);  in dai_dmic_start()
654 static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)  in dai_dmic_stop()  argument
660 	key = k_spin_lock(&dmic->lock);  in dai_dmic_stop()
662 	dai_dmic_stop_fifo_packers(dmic, dmic->dai_config_params.dai_index);  in dai_dmic_stop()
672 	dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
674 		dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
676 		dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
682 			dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,  in dai_dmic_stop()
688 		dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *  in dai_dmic_stop()
689 				     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_stop()
694 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_stop()
701 	const struct dai_intel_dmic *dmic = (const struct dai_intel_dmic *)dev->data;  in dai_dmic_get_properties()  local
704 	prop->fifo_address = dmic->fifo.offset;  in dai_dmic_get_properties()
705 	prop->fifo_depth = dmic->fifo.depth;  in dai_dmic_get_properties()
706 	prop->dma_hs_id = dmic->fifo.handshake;  in dai_dmic_get_properties()
715 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_trigger()  local
726 		if (dmic->state == DAI_STATE_PAUSED ||  in dai_dmic_trigger()
727 		    dmic->state == DAI_STATE_PRE_RUNNING) {  in dai_dmic_trigger()
728 			dai_dmic_start(dmic);  in dai_dmic_trigger()
729 			dmic->state = DAI_STATE_RUNNING;  in dai_dmic_trigger()
732 				dmic->state);  in dai_dmic_trigger()
736 		dai_dmic_stop(dmic, false);  in dai_dmic_trigger()
737 		dmic->state = DAI_STATE_PRE_RUNNING;  in dai_dmic_trigger()
740 		dai_dmic_stop(dmic, true);  in dai_dmic_trigger()
741 		dmic->state = DAI_STATE_PAUSED;  in dai_dmic_trigger()
744 		dai_dmic_gain_ramp(dmic);  in dai_dmic_trigger()
755 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_get_config()  local
765 	*cfg = dmic->dai_config_params;  in dai_dmic_get_config()
774 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_set_config()  local
776 	int di = dmic->dai_config_params.dai_index;  in dai_dmic_set_config()
791 	dai_dmic_program_channel_map(dmic, cfg, di);  in dai_dmic_set_config()
793 	key = k_spin_lock(&dmic->lock);  in dai_dmic_set_config()
799 	ret = dai_dmic_set_config_nhlt(dmic, bespoke_cfg);  in dai_dmic_set_config()
802 	dmic->unmute_time_ms = dmic_get_unmute_ramp_from_samplerate(dmic->dai_config_params.rate);  in dai_dmic_set_config()
812 	dmic->state = DAI_STATE_PRE_RUNNING;  in dai_dmic_set_config()
815 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_set_config()
821 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_probe_wrapper()  local
825 	key = k_spin_lock(&dmic->lock);  in dai_dmic_probe_wrapper()
827 	if (dmic->sref == 0) {  in dai_dmic_probe_wrapper()
828 		ret = dai_dmic_probe(dmic);  in dai_dmic_probe_wrapper()
832 		dmic->sref++;  in dai_dmic_probe_wrapper()
835 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_probe_wrapper()
842 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_remove_wrapper()  local
846 	key = k_spin_lock(&dmic->lock);  in dai_dmic_remove_wrapper()
848 	if (--dmic->sref == 0) {  in dai_dmic_remove_wrapper()
849 		ret = dai_dmic_remove(dmic);  in dai_dmic_remove_wrapper()
852 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_remove_wrapper()