4  * SPDX-License-Identifier: Apache-2.0
33 /* Helper macro to read 64-bit data using two 32-bit data read */
40  * fairly accurately exponent for x in range -2.0 .. +2.0. The iteration
61 		p = num * x; /* Q9.23 x Q3.29 -> Q12.52 */  in exp_small_fixed()
79 	if (x < Q_CONVERT_FLOAT(-11.5, 27)) {  in exp_fixed()
110 	if (db < Q_CONVERT_FLOAT(-100.0, 24)) {  in db2lin_fixed()
120 				 uint32_t reg, uint32_t mask, uint32_t val)  in dai_dmic_update_bits()  argument
122 	uint32_t dest = dmic->reg_base + reg;  in dai_dmic_update_bits()
124 	sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest);  in dai_dmic_update_bits()
130 	sys_write32(val, dmic->reg_base + reg);  in dai_dmic_write()
136 	return sys_read32(dmic->reg_base + reg);  in dai_dmic_read()
143 	sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) |  in dai_dmic_claim_ownership()
144 		    FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_claim_ownership()
150 	sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) &  in dai_dmic_release_ownership()
151 			~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_release_ownership()
164 	return dmic->hdamldmic_base;  in dai_dmic_base()
166 	return dmic->shim_base;  in dai_dmic_base()
173 	uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;  in dai_dmic_set_sync_period()
265 	struct dai_intel_dmic *dmic = ((struct device *)data)->data;  in dai_dmic_irq_handler()
291 	sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),  in dai_dmic_dis_clk_gating()
292 		    dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_dis_clk_gating()
294 	sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD),  in dai_dmic_dis_clk_gating()
295 		    dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_dis_clk_gating()
303 	sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),  in dai_dmic_en_clk_gating()
304 		    dmic->vshim_base + DMICLVSCTL_OFFSET);  in dai_dmic_en_clk_gating()
306 	sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),  in dai_dmic_en_clk_gating()
307 		    dmic->shim_base + DMICLCTL_OFFSET);  in dai_dmic_en_clk_gating()
317 	uint16_t pcmsycm = cfg->link_config;  in dai_dmic_program_channel_map()
318 	uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;  in dai_dmic_program_channel_map()
355 	dmic->state = DAI_STATE_NOT_READY;  in dai_dmic_probe()
369 	irq_enable(dmic->irq);  in dai_dmic_probe()
381 	irq_disable(dmic->irq);  in dai_dmic_remove()
386 	/* The next end tasks must be passed if another DAI FIFO still runs.  in dai_dmic_remove()
388 	 * so it is not needed here to protect access to mask bits.  in dai_dmic_remove()
409 	cfg->walclk_rate = CONFIG_DAI_DMIC_HW_IOCLK;  in dai_dmic_timestamp_config()
424 	cdmas = FIELD_PREP(TS_LOCAL_TSCTRL_CDMAS, cfg->dma_chan_index +  in dai_timestamp_dmic_start()
425 		cfg->dma_chan_count * cfg->dma_id);  in dai_timestamp_dmic_start()
455 	tsd->walclk = sys_read64(TS_DMIC_LOCAL_WALCLK);  in dai_timestamp_dmic_get()
458 	tsd->sample = sys_read64(TS_DMIC_LOCAL_SAMPLE);  in dai_timestamp_dmic_get()
464 	tsd->walclk_rate = cfg->walclk_rate;  in dai_timestamp_dmic_get()
466 		return -ENODATA;  in dai_timestamp_dmic_get()
488 	 * At run-time dmic->gain is only changed in this function, and this  in dai_dmic_gain_ramp()
494 	if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {  in dai_dmic_gain_ramp()
498 	key = k_spin_lock(&dmic->lock);  in dai_dmic_gain_ramp()
503 	dmic->startcount++;  in dai_dmic_gain_ramp()
504 	dmic->gain = q_multsr_sat_32x32(dmic->gain, dmic->gain_coef, Q_SHIFT_GAIN_X_GAIN_COEF);  in dai_dmic_gain_ramp()
509 	gval = dmic->gain >> 11;  in dai_dmic_gain_ramp()
517 		dmic->gain = DMIC_HW_FIR_GAIN_MAX << 11;  in dai_dmic_gain_ramp()
522 		if (!dmic->enable[i]) {  in dai_dmic_gain_ramp()
526 		if (dmic->startcount == DMIC_UNMUTE_CIC) {  in dai_dmic_gain_ramp()
531 		if (dmic->startcount == DMIC_UNMUTE_FIR) {  in dai_dmic_gain_ramp()
533 					     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_gain_ramp()
540 				       dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, val);  in dai_dmic_gain_ramp()
542 				       dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, val);  in dai_dmic_gain_ramp()
545 				       dmic->dai_config_params.dai_index + OUT_GAIN_LEFT,  in dai_dmic_gain_ramp()
546 				       dmic->gain_left);  in dai_dmic_gain_ramp()
548 				       dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT,  in dai_dmic_gain_ramp()
549 				       dmic->gain_right);  in dai_dmic_gain_ramp()
553 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_gain_ramp()
565 	key = k_spin_lock(&dmic->lock);  in dai_dmic_start()
573 	dmic->startcount = 0;  in dai_dmic_start()
576 	dmic->gain_coef = db2lin_fixed(LOGRAMP_CONST_TERM / dmic->unmute_time_ms);  in dai_dmic_start()
579 	dmic->gain = Q_SHIFT_LEFT(db2lin_fixed(LOGRAMP_START_DB), 20, 30);  in dai_dmic_start()
583 	dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index);  in dai_dmic_start()
586 		mic_a = dmic->enable[i] & 1;  in dai_dmic_start()
587 		mic_b = (dmic->enable[i] & 2) >> 1;  in dai_dmic_start()
588 		start_fir = dmic->enable[i] > 0;  in dai_dmic_start()
623 				     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_start()
641 	/* Set bit dai->index */  in dai_dmic_start()
642 	dai_dmic_global.active_fifos_mask |= BIT(dmic->dai_config_params.dai_index);  in dai_dmic_start()
643 	dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_start()
645 	dmic->state = DAI_STATE_RUNNING;  in dai_dmic_start()
646 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_start()
660 	key = k_spin_lock(&dmic->lock);  in dai_dmic_stop()
662 	dai_dmic_stop_fifo_packers(dmic, dmic->dai_config_params.dai_index);  in dai_dmic_stop()
668 	/* Clear bit dmic->dai_config_params.dai_index for active FIFO.  in dai_dmic_stop()
669 	 * If stop for pause, set pause mask bit.  in dai_dmic_stop()
672 	dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
674 		dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
676 		dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);  in dai_dmic_stop()
689 				     dmic->dai_config_params.dai_index + FIR_CONTROL,  in dai_dmic_stop()
694 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_stop()
701 	const struct dai_intel_dmic *dmic = (const struct dai_intel_dmic *)dev->data;  in dai_dmic_get_properties()
702 	struct dai_properties *prop = (struct dai_properties *)dev->config;  in dai_dmic_get_properties()
704 	prop->fifo_address = dmic->fifo.offset;  in dai_dmic_get_properties()
705 	prop->fifo_depth = dmic->fifo.depth;  in dai_dmic_get_properties()
706 	prop->dma_hs_id = dmic->fifo.handshake;  in dai_dmic_get_properties()
707 	prop->reg_init_delay = 0;  in dai_dmic_get_properties()
715 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_trigger()
721 		return -EINVAL;  in dai_dmic_trigger()
726 		if (dmic->state == DAI_STATE_PAUSED ||  in dai_dmic_trigger()
727 		    dmic->state == DAI_STATE_PRE_RUNNING) {  in dai_dmic_trigger()
729 			dmic->state = DAI_STATE_RUNNING;  in dai_dmic_trigger()
731 			LOG_ERR("dmic_trigger(): state is not prepare or paused, dmic->state = %u",  in dai_dmic_trigger()
732 				dmic->state);  in dai_dmic_trigger()
737 		dmic->state = DAI_STATE_PRE_RUNNING;  in dai_dmic_trigger()
741 		dmic->state = DAI_STATE_PAUSED;  in dai_dmic_trigger()
755 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_get_config()
758 		return -EINVAL;  in dai_dmic_get_config()
762 		return -EINVAL;  in dai_dmic_get_config()
765 	*cfg = dmic->dai_config_params;  in dai_dmic_get_config()
774 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_set_config()
776 	int di = dmic->dai_config_params.dai_index;  in dai_dmic_set_config()
783 		return -EINVAL;  in dai_dmic_set_config()
788 		return -EINVAL;  in dai_dmic_set_config()
793 	key = k_spin_lock(&dmic->lock);  in dai_dmic_set_config()
802 	dmic->unmute_time_ms = dmic_get_unmute_ramp_from_samplerate(dmic->dai_config_params.rate);  in dai_dmic_set_config()
812 	dmic->state = DAI_STATE_PRE_RUNNING;  in dai_dmic_set_config()
815 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_set_config()
821 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_probe_wrapper()
825 	key = k_spin_lock(&dmic->lock);  in dai_dmic_probe_wrapper()
827 	if (dmic->sref == 0) {  in dai_dmic_probe_wrapper()
832 		dmic->sref++;  in dai_dmic_probe_wrapper()
835 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_probe_wrapper()
842 	struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;  in dai_dmic_remove_wrapper()
846 	key = k_spin_lock(&dmic->lock);  in dai_dmic_remove_wrapper()
848 	if (--dmic->sref == 0) {  in dai_dmic_remove_wrapper()
852 	k_spin_unlock(&dmic->lock, key);  in dai_dmic_remove_wrapper()
871 		return -ENOTSUP;  in dmic_pm_action()