Lines Matching +full:dac +full:- +full:reference
4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/dac.h>
18 * Maps between the DTS reference property names and register values. Note that
28 Dac *regs;
35 /* Write to the DAC. */
39 const struct dac_sam0_cfg *const cfg = dev->config; in dac_sam0_write_value()
40 Dac *regs = cfg->regs; in dac_sam0_write_value()
44 return -EINVAL; in dac_sam0_write_value()
47 regs->DATA.reg = (uint16_t)value; in dac_sam0_write_value()
59 if (channel_cfg->channel_id != 0) { in dac_sam0_channel_setup()
60 return -EINVAL; in dac_sam0_channel_setup()
62 if (channel_cfg->resolution != 10) { in dac_sam0_channel_setup()
63 return -ENOTSUP; in dac_sam0_channel_setup()
66 if (channel_cfg->internal) { in dac_sam0_channel_setup()
67 return -ENOSYS; in dac_sam0_channel_setup()
73 /* Initialise and enable the DAC. */
76 const struct dac_sam0_cfg *const cfg = dev->config; in dac_sam0_init()
77 Dac *regs = cfg->regs; in dac_sam0_init()
81 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in dac_sam0_init()
84 retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in dac_sam0_init()
90 PM->APBCMASK.reg |= 1 << cfg->pm_apbc_bit; in dac_sam0_init()
92 /* Reset then configure the DAC */ in dac_sam0_init()
93 regs->CTRLA.bit.SWRST = 1; in dac_sam0_init()
94 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
97 regs->CTRLB.bit.REFSEL = cfg->refsel; in dac_sam0_init()
98 regs->CTRLB.bit.EOEN = 1; in dac_sam0_init()
101 regs->CTRLA.bit.ENABLE = 1; in dac_sam0_init()
102 while (regs->STATUS.bit.SYNCBUSY) { in dac_sam0_init()
108 static DEVICE_API(dac, api_sam0_driver_api) = {
114 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference), \
115 (DT_INST_ENUM_IDX(n, reference)), (0))
120 .regs = (Dac *)DT_INST_REG_ADDR(n), \